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220
Revision 1.2
Instruction Set (
Continued
)
G
INC
Increment by 1
Register/Memory
Register (short form)
INT
Software Interrupt
INT i
Protected Mode:
-Interrupt or Trap to Same Privilege
-Interrupt or Trap to Different Privilege
-16-bit Task to 16-bit TSS by Task Gate
-16-bit Task to 32-bit TSS by Task Gate
-16-bit Task to V86 by Task Gate
-16-bit Task to 16-bit TSS by Task Gate
-32-bit Task to 32-bit TSS by Task Gate
-32-bit Task to V86 by Task Gate
-V86 to 16-bit TSS by Task Gate
-V86 to 32-bit TSS by Task Gate
-V86 to Privilege 0 by Trap Gate/Int Gate
INT 3
INTO
If OF==0
If OF==1 (INT 4)
INVD
Invalidate Cache
INVLPG
Invalidate TLB Entry
IRET
Interrupt Return
Real Mode
Protected Mode:
-Within Task to Same Privilege
-Within Task to Different Privilege
-16-bit Task to 16-bit Task
-16-bit Task to 32-bit TSS
-16-bit Task to V86 Task
-32-bit Task to 16-bit TSS
-32-bit Task to 32-bit TSS
-32-bit Task to V86 Task
JB/JNAE/JC
Jump on Below/Not Above or Equal/Carry
8-bit Displacement
Full Displacement
JBE/JNA
Jump on Below or Equal/Not Above
8-bit Displacement
Full Displacement
JCXZ/JECXZ
Jump on CX/ECX Zero
JE/JZ
Jump on Equal/Zero
8-bit Displacement
Full Displacement
JL/JNGE
Jump on Less/Not Greater or Equal
8-bit Displacement
Full Displacement
JLE/JNG
Jump on Less or Equal/Not Greater
8-bit Displacement
Full Displacement
F [111w] [mod 000 r/m]
4 [0 reg]
x
-
-
-
x
x
x
x
-
1
1
1
1
b
h
CD #
-
-
x
0
-
-
-
-
-
19
b,e
g,j,k,r
33
55
184
190
124
187
193
127
187
193
64
INT
CC
CE
INT
4
INT
20
15
4
INT
20
15
0F 08
0F 01 [mod 111 r/m]
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
t
t
CF
x
x
x
x
x
x
x
x
x
13
g,h,j,k,r
20
39
169
175
109
172
178
112
72 +
0F 82 +++
-
-
-
-
-
-
-
-
-
1
1
1
1
r
76 +
0F 86 +++
E3 +
-
-
-
-
-
-
-
-
1
1
2
1
1
2
r
-
-
-
-
-
-
-
-
-
r
74 +
0F 84 +++
-
-
-
-
-
-
-
-
1
1
1
1
r
7C +
0F 8C +++
-
-
-
-
-
-
-
-
1
1
1
1
r
7E +
0F 8E +++
-
-
-
-
-
-
-
-
1
1
1
1
r
Table 7-27. Processor Core Instruction Set Summary (Continued)
Instruction
Opcode
Flags
Real
Mode
Prot’d
Mode
Real
Mode
Prot’d
Mode
O D I
F
F
T
F
S Z
F
A P C
F
F
F
F
F
Clock Count
(Reg/Cache Hit)
Issues