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參數(shù)資料
| 型號(hào)： | 30046-23 |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Low Power Integrated x86-Compatible 32-Bit Geode GXLV Processor(低功耗集成兼容X86的32位 Geode GXLV技術(shù)處理器) |
| 中文描述： | 32-BIT, 200 MHz, MICROPROCESSOR, CPGA320 |
| 封裝： | SPGA-320 |
| 文件頁(yè)數(shù)： | 33/247頁(yè) |
| 文件大小： | 4379K |
| 代理商： | 30046-23 |
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Revision 1.2
33
www.national.com
Signal Definitions (
Continued
)
G
2.2.2
PCI Interface Signals
Signal Name
BGA
Pin No.
SPGA
Pin No
Type
Description
FRAME#
A8
(PU)
C13
(PU)
s/t/s
Frame
FRAME# is driven by the current master to indicate the begin-
ning and duration of an access. FRAME# is asserted to indicate
a bus transaction is beginning. While FRAME# is asserted, data
transfers continue. When FRAME# is deasserted, the transac-
tion is in the final data phase.
This pin is internally connected to a weak (>20-kohm) pull-up
resistor.
IRDY#
C9
(PU)
D14
(PU)
s/t/s
Initiator Ready
IRDY# is asserted to indicate that the bus master is able to com-
plete the current data phase of the transaction. IRDY# is used in
conjunction with TRDY#. A data phase is completed on any
SYSCLK in which both IRDY# and TRDY# are sampled
asserted. During a write, IRDY# indicates valid data is present
on AD[31:0]. During a read, it indicates the master is prepared to
accept data. Wait cycles are inserted until both IRDY# and
TRDY# are asserted together.
This pin is internally connected to a weak (>20-kohm) pull-up
resistor.
TRDY#
B9
(PU)
B14
(PU)
s/t/s
Target Ready
TRDY# is asserted to indicate that the target agent is able to
complete the current data phase of the transaction. TRDY# is
used in conjunction with IRDY#. A data phase is complete on any
SYSCLK in which both TRDY# and IRDY# are sampled
asserted. During a read, TRDY# indicates that valid data is
present on AD[31:0]. During a write, it indicates the target is pre-
pared to accept data. Wait cycles are inserted until both IRDY#
and TRDY# are asserted together.
This pin is internally connected to a weak (>20-kohm) pull-up
resistor.
STOP#
C11
(PU)
A15
(PU)
s/t/s
Target Stop
STOP# is asserted to indicate that the current target is request-
ing the master to stop the current transaction. This signal is used
with DEVSEL# to indicate retry, disconnect or target abort. If
STOP# is sampled active while a master, FRAME# will be deas-
serted and the cycle will be stopped within three SYSCLKs.
STOP# can be asserted in the following cases:
A PCI master tries to access memory that has been locked by
another master. This condition is detected if FRAME# and
LOCK# are asserted during an address phase.
The PCI write buffers are full or a previously buffered cycle
has not completed.
Read cycles that cross cache line boundaries. This is condi-
tional based upon the programming of bit 1 in the PCI Control
Function 2 Register.
This pin is internally connected to a weak (>20-kohm) pull-up
resistor.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 300471U | Radial, -55dotc, long life wsitching-power |
| 300CNQ | SCHOTTKY RECTIFIER |
| 300CNQ035 | SCHOTTKY RECTIFIER |
| 300CNQ040 | SCHOTTKY RECTIFIER |
| 300CNQ045 | SCHOTTKY RECTIFIER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 30046-46L | 制造商:LENOX 功能描述:HOLE SAW BI-METAL 73MM |
| 300-466A | 制造商:LG Corporation 功能描述:CABINET ASSYCMT-9325 |
| 300-466B | 制造商:LG Corporation 功能描述:CABINET ASSYCMT-9324 |
| 300-466K | 制造商:LG Corporation 功能描述:CABINET ASSYCMT-9322 |
| 300-466R | 制造商:LG Corporation 功能描述:FRONT CABINET |
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