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參數(shù)資料
| 型號： | 30046-23 |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Low Power Integrated x86-Compatible 32-Bit Geode GXLV Processor(低功耗集成兼容X86的32位 Geode GXLV技術(shù)處理器) |
| 中文描述： | 32-BIT, 200 MHz, MICROPROCESSOR, CPGA320 |
| 封裝： | SPGA-320 |
| 文件頁數(shù)： | 182/247頁 |
| 文件大?。?/td> | 4379K |
| 代理商： | 30046-23 |
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182
Revision 1.2
Power Management (
Continued
)
G
GX_BASE+8504h-8507h
PM_CNTRL_TEN Register (R/W)
Default Value = xxxxxx00h
31:8
7:6
5
RSVD
RSVD
Reserved:
These bits are not used. Do not write to these bits.
Reserved:
Set to 0.
Transmission Test (Write Only)
: Setting this bit causes the GXLV processor to immediately trans-
mit the current contents of the serial packet. This bit is write only and is used primarily for test. This
bit returns 0 on a read.
Transmission Frequency:
This field indicates the time between serial packet transmissions. Serial
packet transmissions occur at the selected interval only if at least one of the packet bits is set high:
00 = Disable transmitter; 01 = 1 ms; 10 = 5 ms; 11 = 10 ms.
CPU Activity Read Enable:
Setting this bit high enables reporting of CPU level-1 cache read
misses that are not a result of an instruction fetch. This bit is a don
’
t-care if the CPU_EN bit is not set
high.
CPU Activity Master Enable:
Setting this bit high enables reporting of CPU Level-1 cache misses
in bit 6 of the serial transmission packet. When enabled, the CPU Level-1 cache miss activity is
reported on any read (assuming the CPU_RD is set high) or write access excluding misses that
resulted from an instruction fetch.
Video Event Enable:
Setting this bit high enables video decode events to be reported in bit 0 of the
serial transmission packet. CPU or graphics-pipeline accesses to the graphics memory and display-
controller-register accesses are also reported.
X_TEST (WO)
4:3
X_FREQ
2
CPU_RD
1
CPU_EN
0
VID_EN
GX_BASE+8508h-850Bh
PM_CNTRL_CSTP Register (R/W)
Default Value = xxxxxx00h
31:8
7:1
0
RSVD
RSVD
CLK_STP
Reserved:
These bits are not used. Do not write to these bits.
Reserved:
Set to 0.
Clock Stop:
This bit configures the GXLV processor for Suspend Refresh Mode or 3 Volt Suspend
Mode:
0 = Suspend Refresh Mode. The clocks to the memory and display controller remain active during
Suspend.
1 = 3 Volt Suspend Mode. The external clock may be stopped during Suspend.
Note:
When bit 0 is set high and the Suspend input pin (SUSP#) is asserted, the GXLV processor stops all it
’
s internal clocks, and
asserts the Suspend Acknowledge output pin (SUSPA#). Once SUSPA# is asserted the GXLV processor
’
s SYSCLK input can
be stopped. If bit 0 is cleared, the internal memory-controller and display-controller clocks are not stopped on the
SUSP#/SUSPA# sequence, and the SYSCLK input can not be stopped.
GX_BASE+850Ch-850Fh
PM_SER_PACK Register (R/O)
Default Value = xxxxxx00h
31:8
7
RSVD
VID_IRQ
Reserved:
These bits are not used. Do not write to these bits.
Video IRQ:
This bit indicates the occurrence of a video vertical sync pulse. This bit is set at the
same time that the VINT (Vertical Interrupt) bit is set in the DC_TIMING_CFG register. The VINT bit
has a corresponding enable bit (VIEN) in the DC_TIM_CFG register (See Table 4-29 on page 145).
CPU Activity:
This bit indicates the occurrence of a level 1 cache miss that was not a result of an
instruction fetch. This bit has a corresponding enable bit in the PM_CNTL_TEN register.
Reserved:
Set to 0.
Programmable Address Decode:
This bit indicates the occurrence of a programmable memory
address decode. This bit is set based on the values of the PM_BASE register and the PM_MASK
register (see Table 5-3 on page 183). The PM_BASE register can be initialized to any address in the
full 256 MB address range.
Video Decode:
This bit indicates that the CPU has accessed either the Display Controller registers
or the graphics memory region. This bit has a corresponding enable bit in the PM_CNTRL_TEN.
Note:
The GXLV processor transmits the contents of the serial packet only when a bit in the packet register is set and the interval
counter has elapsed. The Geode I/O companion decodes the serial packet after each transmission. Once a bit in the packet is
set, it will remain set until the completion of the next packet transmission. Successive events of the same type that occur
between packet transmissions are ignored. Multiple unique events between packet transmissions will accumulate in this regis-
ter.
6
CPU_ACT
5:2
1
RSVD
USR_DEF
0
VID_DEC
Table 5-2. Power Management Control and Status Registers (Continued)
Bit
Name
Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 300471U | Radial, -55dotc, long life wsitching-power |
| 300CNQ | SCHOTTKY RECTIFIER |
| 300CNQ035 | SCHOTTKY RECTIFIER |
| 300CNQ040 | SCHOTTKY RECTIFIER |
| 300CNQ045 | SCHOTTKY RECTIFIER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 30046-46L | 制造商:LENOX 功能描述:HOLE SAW BI-METAL 73MM |
| 300-466A | 制造商:LG Corporation 功能描述:CABINET ASSYCMT-9325 |
| 300-466B | 制造商:LG Corporation 功能描述:CABINET ASSYCMT-9324 |
| 300-466K | 制造商:LG Corporation 功能描述:CABINET ASSYCMT-9322 |
| 300-466R | 制造商:LG Corporation 功能描述:FRONT CABINET |
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