Revision 1.2
231
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Instruction Set (
Continued
)
G
FNOP
No Operation
FPATAN
Function Eval: Tan
-1
(y/x)
D9 D0
No Operation
2
D9 F3
ST(1) <--- ATAN[ST(1) / TOS]; then pop TOS
97 - 161
3
FPREM
Floating Point Remainder
D9 F8
TOS <--- Rem[TOS / ST(1)]
82 - 91
FPREM1
Floating Point Remainder IEEE
D9 F5
TOS <--- Rem[TOS / ST(1)]
82 - 91
FPTAN
Function Eval: Tan(x)
D9 F2
TOS <--- TAN(TOS); then push 1.0 onto stack
117 - 129
1
FRNDINT
Round to Integer
D9 FC
TOS <--- Round(TOS)
10 - 20
FRSTOR
Load FPU Environment and Register
DD [mod 100 r/m]
Restore state
56 - 72
FSAVE
Save FPU Environment and Register
(9B)DD [mod 110 r/m]
Wait, then save state
57 - 67
FNSAVE
Save FPU Environment and Register
FSCALE
Floating Multiply by 2
n
DD [mod 110 r/m]
Save state
TOS <--- TOS
×
2
(ST(1))
TOS <--- SIN(TOS)
55 - 65
D9 FD
7 - 14
FSIN
Function Evaluation: Sin(x)
D9 FE
76 - 140
1
FSINCOS
Function Eval.: Sin(x)& Cos(x)
D9 FB
temp <--- TOS;
TOS <--- SIN(temp); then
push COS(temp) onto stack
145 - 161
1
FSQRT
Floating Point Square Root
D9 FA
TOS <--- Square Root of TOS
59 - 60
FST
Store FPU Register
Top of Stack
DD [1101 0 n]
ST(n) <--- TOS
2
64-bit Real
DD [mod 010 r/m]
M.DR <--- TOS
2
32-bit Real
D9 [mod 010 r/m]
M.SR <--- TOS
2
FSTP
Store FPU Register, Pop
Top of Stack
DB [1101 1 n]
ST(n) <--- TOS; then pop TOS
2
80-bit Real
DB [mod 111 r/m]
M.XR <--- TOS; then pop TOS
2
64-bit Real
DD [mod 011 r/m]
M.DR <--- TOS; then pop TOS
2
32-bit Real
D9 [mod 011 r/m]
M.SR <--- TOS; then pop TOS
2
FBSTP
Store BCD Data, Pop
DF [mod 110 r/m]
M.BCD <--- TOS; then pop TOS
57 - 63
FIST
Store Integer FPU Register
32-bit Integer
DB [mod 010 r/m]
M.SI <--- TOS
8 - 13
16-bit Integer
DF [mod 010 r/m]
M.WI <--- TOS
7 - 10
FISTP
Store Integer FPU Register, Pop
64-bit Integer
DF [mod 111 r/m]
M.LI <--- TOS; then pop TOS
10 - 13
32-bit Integer
DB [mod 011 r/m]
M.SI <--- TOS; then pop TOS
8 - 13
16-bit Integer
DF [mod 011 r/m]
M.WI <--- TOS; then pop TOS
7 - 10
FSTCW
Store FPU Mode Control Register
(9B)D9 [mod 111 r/m]
Wait Memory <--- Control Mode Register
5
FNSTCW
Store FPU Mode Control Register
D9 [mod 111 r/m]
Memory <--- Control Mode Register
3
FSTENV
Store FPU Environment
(9B)D9 [mod 110 r/m]
Wait Memory <--- Env. Registers
14 - 24
FNSTENV
Store FPU Environment
D9 [mod 110 r/m]
Memory <--- Env. Registers
12 - 22
FSTSW
Store FPU Status Register
(9B)DD [mod 111 r/m]
Wait Memory <--- Status Register
6
FNSTSW
Store FPU Status Register
DD [mod 111 r/m]
Memory <--- Status Register
4
FSTSW AX
Store FPU Status Register to AX
(9B)DF E0
Wait AX <--- Status Register
4
FNSTSW AX
Store FPU Status Register to AX
DF E0
AX <--- Status Register
2
FSUB
Floating Point Subtract
Top of Stack
DC [1110 1 n]
ST(n) <--- ST(n) - TOS
4 - 9
80-bit Register
D8 [1110 0 n]
TOS <--- TOS - ST(n
4 - 9
64-bit Real
DC [mod 100 r/m]
TOS <--- TOS - M.DR
4 - 9
32-bit Real
D8 [mod 100 r/m]
TOS <--- TOS - M.SR
4 - 9
FSUBP
Floating Point Subtract, Pop
DE [1110 1 n]
ST(n) <--- ST(n) - TOS; then pop TOS
4 - 9
FSUBR
Floating Point Subtract Reverse
Top of Stack
DC [1110 0 n]
TOS <--- ST(n) - TOS
4 - 9
80-bit Register
D8 [1110 1 n]
ST(n) <--- TOS - ST(n)
4 - 9
64-bit Real
DC [mod 101 r/m]
TOS <--- M.DR - TOS
4 - 9
32-bit Real
D8 [mod 101 r/m]
TOS <--- M.SR - TOS
4 - 9
Table 7-29. FPU Instruction Set Summary (Continued)
FPU Instruction
Opcode
Operation
Clock
Count
Issue