參數(shù)資料
型號： 38D5
廠商： Renesas Technology Corp.
英文描述： SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
中文描述： 單芯片8位CMOS微機
文件頁數(shù)： 136/141頁
文件大?。?/td> 2027K
代理商： 38D5
(2/6)
REVISION HISTORY
38D5 Group Data Sheet
2.00
Jan 23, 2006
71
Table 14 Recommended operating conditions
- Vcc (Power source voltage) and Note revised.
- V
IH
, V
IL
(RESET) revised.
73
Table 16 Recommended operating conditions: all revised, Power source voltage
graph added.
Table 17 Electrical characteristics: ROSC
→
f(OCO)
74
75
Table 18 Electrical characteristics: Icc revised.
Table 19 A/D converter recommended operating condition revised.
76
Table 20 A/D converter characteristics: test conditions revised.
AD Power source voltage graph added.
77
Table 21 Timing requirements 1: t
c
(X
IN
), t
wH
(X
IN
), t
wL
(X
IN
) revised and Note added.
81
PACKAGE OUTLINE revised.
2.01
Mar 24, 2006
1
FEATURES: Power source voltage revised.
4
Performance overview: Oscillation frequency and Power source voltage revised.
17
Table 7 Related SFRs of port P7 revised.
52
Fig. 46: Address revised.
53
Fig. 50: Note 1 revised.
58
(1)Stop mode: Description revised.
Fig. 59
φ
SOURCE
added.
59
60
Fig. 60 State transitions of system clock: Note 3 revised.
71
Table 14 : Vcc (Power source voltage) and Note 3 revised.
73
Table 16: Power source voltage (Main clock X
IN
frequency) graph added.
76
Table 20 Description of f(OCO) and Note revised.
2.02
Jul 10, 2006
15
Fig. 11: Register names of ROM correction addresses 1 and 2 revised.
22
Termination of unused pins I/O ports : Description added.
23
Table 8
Termination 1 (recommended) : Delete (recommended).
Termination 1 to 3 of P7
0
/C
1
/INT
01
and P7
1
/C
2
/INT
11
: revised.
29
X
CIN
is selected as Timer 1, 2 count source : sentence is revised.
32
X
CIN
is selected as Timer X count source : sentence is revised.
Fig. 26: (TXCON1 bit 5 = “1”)
→
(TXCON1 bit 5 = “0”)
33
35
X
CIN
is selected as Timer Y count source : sentence is revised.
43
Fig. 38:
φ
SOURCE
clock added.
52
Fig. 47: Border line in ROM area : revised.
Fig. 49: On chip oscillator
→
On chip oscillator/4
Fig. 50: b5 and b7 revised.
53
58
Frequency Control : Description added.
61
Table 12: Function of V
REF
and AV
SS
revised.
64 to 67
Fig. 63 to Fig. 66: Revised and added.
76
Table 17: Parameter of I
IH
and I
IC
added.
2.03
Aug 31, 2006
4
Table 1: Main clock and Sub-clock generating circuit : “feedback resistor”
eliminated.
Table 3: AV
SS
: GND
→
Analog power source
Table 8: P4
1
/TxD : input port
→
output port
P4
2
/S
CLK1
: output port
→
input port
7
23
Rev.
Date
Description
Page
Summary
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