參數(shù)資料
型號(hào)： 38D5
廠商： Renesas Technology Corp.
英文描述： SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
中文描述： 單芯片8位CMOS微機(jī)
文件頁數(shù)： 15/141頁
文件大?。?/td> 2027K
代理商： 38D5
Rev.3.01
REJ03B0158-0301
Aug 08, 2007
Page 15 of 134
38D5 Group
[CPU Mode Register (CPUM)] 003B
16
The CPU mode register contains the stack page selection bit, etc.
This register is allocated at address 003B
16
.
After the system is released from reset, the mode depends on the
OSCSEL pin state in the QzROM version.
When the OSCSEL pin state is GND level, only the on-chip
oscillator starts oscillation. The X
IN
-X
OUT
oscillation stops
oscillating, and X
CIN
and X
COUT
pins function as I/O ports. The
operating mode is the on-chip oscillator mode.
When the OSCSEL pin state is Vcc level, the X
IN
-X
OUT
oscillation divided by 8 starts oscillation. The on-chip oscillator
stops oscillating, and the X
CIN
and X
COUT
pins function as I/O
ports. The operating mode is the frequency/8 mode.
In the flash memory version, only the on-chip oscillator starts
oscillating. The X
IN
-X
OUT
oscillation stops oscillating, and the
X
CIN
and X
COUT
pins function as I/O ports. The operating mode
is the on-chip oscillator mode.
When the main clock or sub-clock is used, after the X
IN
-X
OUT
oscillation and the X
CIN
-X
COUT
oscillation are enabled, wait in
the on-chip oscillator mode etc. until the oscillation stabilizes,
and then switch the operation mode.
When the main clock is not used (X
IN
-X
OUT
oscillation and an
external clock input are not used), connect the X
IN
pin to V
CC
through a resistor and leave X
OUT
open.
[CPU Mode Register 2 (CPUM2)] 0011
16
The CPU mode register 2 contains the control bits for the on-chip
oscillator.
The CPU mode register 2 is allocated at address 0011
16
.
Fig. 8 Structure of CPU mode register
On-chip oscillator stop bit
0 : Oscillating
1 : Stopped
Not used (do not write “1”)
Not used (returns “0” when read)
Not used (do not write “1”)
Processor mode bits
b1 b0
0 0 : Single-chip mode
0 1 :
1 0 :
1 1 :
Stack page selection bit
0 : 0 page
1 : 1 page
Internal system clock selection bit
0 : Main clock selected
(includes OCO, X
IN
)
1 : X
CIN
–X
COUT
selected
Port Xc switch bit
0 : I/O port function (Oscillation stop)
1 : X
CIN
–X
COUT
oscillating function
X
IN
–X
OUT
oscillation stop bit
0 : Oscillating
1 : Stopped
Main clock division ratio selection bit
(Valid only when CM3=0)
b7 b6
0 0 : f(X
IN
)/2 (frequency/2 mode)
0 1 : f(X
IN
)/8 (frequency/8 mode)
1 0 : f(X
IN
)/4 (frequency/4 mode)
1 1 : On-chip oscillator
b7
b0
CPU mode register 2
CPUM2
(address 0011
16
, QzROM version, OSCSEL=L, initial value: 00
16
)
(
QzROM version, OSCSEL=H, initial value: 01
16
)
(
Flash memory version,
initial value: 00
16
)
CM8
b7
b0
CPU mode register
CPUM
(address 003B
16
,QzROM version, OSCSEL=L, initial value: E0
16
)
(
QzROM version, OSCSEL=H, initial value: 40
16
)
(
Flash memory version,
initial value: E0
16
)
CM0
CM1
CM2
CM3
CM4
CM5
CM6
CM7
Not available
Notes 1
: When the on-chip oscillator is selected by the watchdog timer count source selection bit 2 (bit
5 of watchdog timer control register (address 0029
16
)), the on-chip oscillator does not stop
even when the on-chip oscillator stop bit is set to “1”.
Also, when the low-speed mode is set, the on-chip oscillator stops regardless of the value of
this bit in the QzROM version. The on-chip oscillator does not stop in the flash memory
version, so set this bit to “1” to stop the oscillation.
In on-chip oscillator mode, even if this bit is set to “1”, the on-chip oscillator does not stop in
the flash memory version, but stops in the QzROM version.
2
: In low-speed mode, the X
CIN
-X
COUT
oscillation stops if the port X
C
switch bit is set to “0”.
3
: In X
IN
mode, the X
IN
-X
OUT
oscillation does not stop even if the X
IN
-X
OUT
oscillation stop bit is
set to “1”.
4
: 12.5 MHz < f(X
IN
)
≤
16 MHz is not available in the frequency/2 mode.
(
1
)
(
4
)
(
2
)
(
3
)
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