參數(shù)資料
型號: 38D5
廠商: Renesas Technology Corp.
英文描述: SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
中文描述: 單芯片8位CMOS微機
文件頁數(shù): 60/141頁
文件大?。?/td> 2027K
代理商: 38D5
Rev.3.01
REJ03B0158-0301
Aug 08, 2007
Page 60 of 134
38D5 Group
RESET CIRCUIT
To reset the microcomputer, RESET pin should be held at an “L”
level for 2
μ
s or more. Then the RESET pin is returned to an “H”
level (the power source voltage should be between V
CC
(min.)
and 5.5 V), reset is released.
After the reset is completed, the program starts from the address
contained in address FFFD
16
(high-order byte) and address
FFFC
16
(low-order byte). Make sure that the reset input voltage
meets V
IL
spec. When a power source voltage passes V
CC
(min.).
In the flash memory version, input to the RESET pin in the
following procedure.
When power source is stabilized
(1) Input “L” level for 2
μ
s or more to RESET pin.
(2) Input “H” level to RESET pin.
At power-on
(1) Input “L” level to RESET pin.
(2) Increase the power source voltage to 2.7 V.
(3) Wait for td(P-R) until internal power source has stabilized.
(4) Input “H” level to RESET pin.
In the QzROM version, the input level applied to the OSCSEL
pin is determined when the RESET pin changes from “L” to “H”.
Fig. 57 Reset circuit example
Fig. 58 Reset sequence
V
CC
Power source
voltage detection
circuit
RESET
V
CC
RESET
0 V
0 V
VCC
RESET
0.2V
CC
or less
0 V
5 V
0 V
V
CC
RESET
td(P-R) or more
5 V
2.7 V
(1)
Note 1
: QzROM version: 2
μ
s or more
Flash memory version: td(P-R) or more
V
CC
(min.)
RESET
Internal
reset
Address
Data
SYNC
System clock
φ
OSCSEL=L: OCO
OSCSEL=H: X
IN
FFFC
FFFD
AD
H,
AD
L
AD
L
AD
H
Reset address from
······
OSCSEL=L: OCO= about 32768 cycles
OSCSEL=H: X
IN
= about 8192 cycles
Notes 1
: The frequency of system clock
φ
is f(OCO)/32 or f(X
IN
)/8.
2
: The question marks () indicate an undefined state.
3
: In the QzROM version, the input level applied to the OSCSEL pin is determined when the RESET pin changes from “L” to “H”.
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