參數(shù)資料
型號(hào)： 38D5
廠商： Renesas Technology Corp.
英文描述： SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
中文描述： 單芯片8位CMOS微機(jī)
文件頁(yè)數(shù)： 19/141頁(yè)
文件大小： 2027K
代理商： 38D5
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Rev.3.01
REJ03B0158-0301
Aug 08, 2007
Page 19 of 134
38D5 Group
I/O PORTS
Direction Registers (Ports P0-P6, P7
2
-P7
4
)
The I/O ports P0-P6, P7
2
-P7
4
have direction registers which
determine the input/output direction of each individual pin. Each
bit in a direction register corresponds to one pin, each pin can be
set to be input port or output port.
When “0” is written to the bit of the direction register, the
corresponding pin becomes an input pin. As for ports P0
P3,
when “1” is written to the bit of the direction register and the
segment output disable register, the corresponding pin becomes
an output pin. As for ports P4
P6, P7
2
-P7
4
when “1” is written to
the bit of the direction register, the corresponding pin becomes an
output pin.
If data is read from a pin set to output, the value of the port latch
is read, not the value of the pin itself. However, when peripheral
output (RTP
1
, RTP
0
, T
XOUT1
, T
XOUT2
, T
4OUT
, T
3OUT
and
T
2OUT
/CKOUT) is selected, the output value is read. Depending
on the pin, output from a peripheral function may be read. Pins
set to input are floating. If a pin set to input is written to, only the
port output latch is written to and the pin remains floating.
Ports P7
0
, P7
1
These are input ports which are shared with the voltage
multiplier. When these are read out at using the voltage
multiplier, the contents are “1”.
Pull-up Control
Each individual bit of ports P0
P3 can be pulled up with a
program by setting direction registers and segment output disable
registers 0 to 2 (addresses 0FF4
16
to 0FF6
16
).
The pin is pulled up by setting “0” to the direction register and
“1” to the segment output disable register.
By setting the PULL registers (addresses 0FF0
16
to OFF2
16
),
ports P4
P7 can control pull-up with a program.
However, the contents of PULL register do not affect ports
programmed as the output ports.
Fig. 12 Structure of ports P0 to P3
Fig. 13 Structure of PULL register and segment output
disable register
Segment output
disable register
Direction
register
Input port
No pull-up
Input port
Pull-up
Segment
output
Port output
“0”
“0”
“1”
“1”
Initial state
Note1
: The PULL register and segment output disable register affect only ports
programmed as the input ports.
P6
0
pull-up
P6
1
pull-up
P6
2
pull-up
P6
3
pull-up
P6
4
pull-up
P6
5
pull-up
P6
6
pull-up
P6
7
pull-up
PULL register 2
(PULL2 : address 0FF1
16
))
b7
b0
PULL register 1
(PULL1 : address 0FF0
16
)
b7
b0
P5
0
pull-up
P5
1
pull-up
P5
2
pull-up
P5
3
pull-up
P5
4
pull-up
P5
5
pull-up
P5
6
pull-up
P5
7
pull-up
P4
0-
P4
3
pull-up
P4
4-
P4
7
pull-up
P7
2-
P7
4
pull-up
Not used (do not write “1”)
Not used (return “0” when read)
PULL register 3
(PULL3 : address 0FF2
16
))
b7
b0
P0
0
pull-up
P0
1
pull-up
P0
2
pull-up
P0
3
pull-up
P0
4
pull-up
P0
5
pull-up
P0
6
pull-up
P0
7
pull-up
Segment output disable register 0
(SEG0 : address 0FF4
16
)
b7
b0
0 : No pull-up
1 : Pull-up
0 : No pull-up
1 : Pull-up
0 : No pull-up
1 : Pull-up
0 : No pull-up
1 : Pull-up
P2
0
pull-up
P2
1
pull-up
P2
2
pull-up
P2
3
pull-up
P2
4
pull-up
P2
5
pull-up
P2
6
pull-up
P2
7
pull-up
Segment output disable register 1
(SEG1 : address 0FF5
16
)
b7
b0
0 : No pull-up
1 : Pull-up
P1
0-
P1
3
pull-up
P1
4-
P1
7
pull-up
P3
0-
P3
3
pull-up
P3
4-
P3
7
pull-up
Not used (do not write “1”)
Segment output disable register 2
(SEG2 : address 0FF6
16
)
b7
b0
0 : No pull-up
1 : Pull-up
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