參數(shù)資料
型號： 38D5
廠商： Renesas Technology Corp.
英文描述： SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
中文描述： 單芯片8位CMOS微機
文件頁數(shù)： 138/141頁
文件大?。?/td> 2027K
代理商： 38D5
(4/6)
REVISION HISTORY
38D5 Group Data Sheet
2.04
Feb 02, 2007
81
t
h
(S
CLK2
-R
X
D)
→
t
h
(S
CLK2
-S
IN2
)
Table 23
Limits of t
wH
(S
CLK2
), t
wL
(S
CLK2
): t
c
(S
CLK1
)/2–30
→
t
c
(S
CLK2
)/2–30
3.01
Aug 08, 2007
38D5 Group (Flash Memory Version For Development) Datasheet (No.
REJ03B0197) is merged.
1
Flash memory version contents: added
DESCRIPTION: Description added
Memory size (QzROM version): 640 bytes
→
1536 bytes
Power dissipation (Flash memory version): revised
2
Fig. 1: Flash memory version: “M38D59FFFP” added, Notes: added
3
Fig. 2: Flash memory version: “M38D59FFHP” added, Notes: added
4
Table 1: Flash memory version contents: added and separates to Table 2 (Next
page)
Memory size (QzROM version); 640 bytes
→
1536 bytes
I/O port; 32 pins
→
36 pins
7
Table 3: I/O port P3, I/O port P4: revised
Table 4: OSCSEL
→
CNV
SS
/function: revised
8
9
Fig.4 “Memory type”: Flash memory version added
10
Memory Type: deleted
Memory size (QzROM version): 640 bytes
→
1536 bytes
Fig. 5: Under development products
→
mass-produced
Table 5: Flash memory version products added
11
Table 6, Notes on Differences between QzROM and Flash Memory Versions: added
12
Central Processing Unit: revised
15
Fig. 8: Flash memory version contents: added
Notes: revised
16
Fig. 9: Flash memory version contents: added
Low/X
IN
mode
→
Low-speed/X
IN
mode
17
Memory: Flash memory version contents: added
ROM is revised
ROM code Protect Address in QzROM version is revised
Fig. 10: revised
18
Fig. 11: revised
Fig. 13: Do not write “1”
→
Not used (do not write “1”)
19
23
Fig. 16 (14) Port P6
0
: Revised port Xc switch bit input to low-active
27 to 31
INTERRUPTS: revised
Interrupt Source Selection: interrupt source selection register
→
interrupt edge
selection register
External Interrupt Pin Selection: INT
0
, INT
1
interrupt switch bit
→
INT
0
, INT
1
input
port switch bit
Fig. 19: Do not write “1”
→
Not used (do not write “1”)
<Notes>: Related registers
→
Related bits, and its explain is revised
28
29
31
34
Fig. 25: Figure title is revised
P7
2
clock output control bit block is revised
Frequency Divided For Timer: revised
<Notes on Timer 1 to Timer 4>: (2)Writing to Timer 2, Timer 3, Timer 4
→
(2)Write
Timer 2, Timer 3, Timer4
35
37
Fig. 28: Figure title is revised
Timer X output 1 edge switch bit
→
Timer X output 1 active edge switch bit
Rev.
Date
Description
Page
Summary
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