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參數(shù)資料
| 型號(hào)： | 38D5 |
| 廠商： | Renesas Technology Corp. |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| 中文描述： | 單芯片8位CMOS微機(jī) |
| 文件頁數(shù)： | 48/141頁 |
| 文件大小： | 2027K |
| 代理商： | 38D5 |
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Rev.3.01
REJ03B0158-0301
Aug 08, 2007
Page 48 of 134
38D5 Group
[Serial I/O2 Operation]
Writing to the serial I/O2 register initializes the serial I/O2
counter to “7”.
After writing, the S
OUT2
pin outputs data each time the
synchronous clock changes from “H” to “L”. The S
IN2
pin
captures data each time the synchronous clock changes from “L”
to “H” and the serial I/O2 register shifts 1-bit simultaneously.
When the external clock is selected as the synchronous clock,
counting the synchronous clock eight times results the following:
Serial I/O2 counter = “0”
Synchronous clock is stopped at “H”
Serial I/O2 interrupt request bit = “1”
After transfer is completed, the S
OUT2
pin is placed in the high-
impedance state.
When the external clock is selected as the synchronous clock,
counting the synchronous clock eight times sets the serial I/O2
bit to “1” and the S
OUT2
pin retains the D7 output level.
However, if the synchronous clock is continuously input, the
serial I/O2 register continues shifting and the S
OUT2
pin keeps
outputting transmit data.
Fig. 40 Serial I/O2 timing
D
0
D
1
D
2
D
3
D
4
D
5
D
6
Serial I/O2 interrupt request bit set
Transfer clock
Serial I/O2 register
write signal
Serial I/O2 input S
IN2
Notes 1
: When the internal clock is selected as the transfer, the dividing frequency of internal clock for transfer
clock can be selected by bits 0 to 2 of serial I/O2 control register.
2
: When the internal clock is selected as the synchronous clock, the S
OUT2
pin is placed in the high
impedance state after transfer is completed.
3
: When the external clock is selected as the synchronous clock, the S
OUT2
pin retains the D
7
output level
after transfer is completed.
However, if the synchronous clock is continuously input, the serial I/O2 register continues shifting and the
S
OUT2
pin keeps outputting transmit data.
D
7
Serial I/O2 output S
OUT2
(1)
(2) (3)
Reception enable signal
S
RDY2
(When the internal clock
is selected)
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