參數(shù)資料
型號： 38D5
廠商： Renesas Technology Corp.
英文描述： SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
中文描述： 單芯片8位CMOS微機(jī)
文件頁數(shù)： 36/141頁
文件大?。?/td> 2027K
代理商： 38D5
Rev.3.01
REJ03B0158-0301
Aug 08, 2007
Page 36 of 134
38D5 Group
Fig. 27 Structure of Timer 1 to timer 4 related registers
Timer 12 mode register
(T12M: address 0025
16
)
Timer 34 mode register
(T34M: address 0026
16
)
Timer 3 count stop bit
0 : Count operation
1 : Count stop
Timer 4 count stop bit
0 : Count operation
1 : Count stop
Timer 1234 mode register
(T1234M: address 0027
16
)
T
3OUT
output edge switch bit
0 : Start at “L” output
1 : Start at “H” output
T
4OUT
output edge switch bit
0 : Start at “L” output
1 : Start at “H” output
Timer 1234 frequency division selection register
(PRE1234: address 0028
16
)
PWM01 register
(PWM01: address 0024
16
)
Timer 1 frequency division selection bits
b1b0
0 0 : 1/16
×
φ
SOURCE
0 1 : 1/1
×
φ
SOURCE
1 0 : 1/2
×
φ
SOURCE
1 1 : 1/256
×
φ
SOURCE
Timer 2 frequency division selection bits
b3b2
0 0 : 1/16
×
φ
SOURCE
0 1 : 1/1
×
φ
SOURCE
1 0 : 1/2
×
φ
SOURCE
1 1 : 1/256
×
φ
SOURCE
Timer 3 frequency division selection bits
b5b4
0 0 : 1/16
×
φ
SOURCE
0 1 : 1/1
×
φ
SOURCE
1 0 : 1/2
×
φ
SOURCE
1 1 : 1/256
×
φ
SOURCE
Timer 1 count stop bit
0 : Count operation
1 : Count stop
T
2OUT
output edge switch bit
0 : Start at “L” output
1 : Start at “H” output
Timer 2 output selection bit (P7
2
)
0 : I/O port
1 : Timer 2 output
Timer 2 count source selection bits
b5b4
0 0 : Underflow of Timer 1
0 1 : f(X
CIN
)
1 0 : Frequency divider for Timer 2
1 1 : Not available
Timer 1 count source selection bits
b3b2
0 0 : Frequency divider for Timer 1
0 1 : f(X
CIN
)
1 0 : Underflow of Timer Y
1 1 : Not available
Timer 2 count stop bit
0 : Count operation
1 : Count stop
PWM0 set bits
b1b0
0 0 : No extended
0 1 : Extended once in four periods
1 0 : Extended twice in four periods
1 1 : Extended three times in four periods
PWM1 set bits
b3b2
0 0 : No extended
0 1 : Extended once in four periods
1 0 : Extended twice in four periods
1 1 : Extended three times in four periods
Not used (returns “0” when read)
Timer 4 frequency division selection bits
b7b6
0 0 : 1/16
×
φ
SOURCE
0 1 : 1/1
×
φ
SOURCE
1 0 : 1/2
×
φ
SOURCE
1 1 : 1/256
×
φ
SOURCE
Not used (returns “0” when read)
Timer 4 write control bit
0 : Write data to both timer latch and timer
1 : Write data to timer latch only
Timer 3 write control bit
0 : Write data to both timer latch and timer
1 : Write data to timer latch only
Timer 2 write control bit
0 : Write data to both timer latch and timer
1 : Write data to timer latch only
Timer 4 output selection bit (P7
4
)
0 : I/O port
1 : Timer 4 output
Timer 3 output selection bit (P7
3
)
0 : I/O port
1 : Timer 3 output
Not used (returns “0” when read)
Timer 4 operating mode selection bit
0 : Timer mode
1 : PWM mode
Timer 3 operating mode selection bit
0 : Timer mode
1 : PWM mode
Timer 4 count source selection bits
b4b3
0 0 : Frequency divider for Timer 4
0 1 : Underflow of Timer 3
1 0 : Underflow of Timer 2
1 1 : f(X
IN
)
Timer 3 count source selection bit
0 : Frequency divider for Timer 3
1 : Underflow of Timer 2
b7
b0
b7
b0
b7
b0
b7
b0
b7
b0
Note1:
φ
SOURCE indicates the followings:
X
IN
input in the frequency/2, 4, or 8 mode
On-chip oscillator divided by 4 in the on-chip oscillator mode
Sub-clock in the low-speed mode
(1)
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