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參數(shù)資料
| 型號： | 38D5 |
| 廠商： | Renesas Technology Corp. |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| 中文描述： | 單芯片8位CMOS微機 |
| 文件頁數(shù)： | 44/141頁 |
| 文件大小： | 2027K |
| 代理商： | 38D5 |
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Rev.3.01
REJ03B0158-0301
Aug 08, 2007
Page 44 of 134
38D5 Group
(2) Asynchronous Serial I/O (UART) Mode
Clock asynchronous serial I/O mode (UART) can be selected by
setting the serial I/O mode selection bit of the serial I/O1 control
register to “0”.
Eight serial data transfer formats can be selected, and the transfer
formats used by a transmitter and receiver must be identical.
The transmit and receive shift registers each have a buffer, but
the two buffers have the same address in memory. Since the shift
register cannot be written to or read from directly, transmit data
is written to the transmit buffer register, and receive data is read
from the receive buffer register.
The transmit buffer register can also hold the next data to be
transmitted, and the receive buffer register can hold a character
while the next character is being received.
Fig. 35 Block diagram of UART serial I/O1
Fig. 36 Operation of UART serial I/O1 function
1/4
OE
PE FE
1/16
1/16
Data bus
Receive buffer register
Receive shift register
Receive buffer full flag (RBF)
Receive interrupt request (RI)
Baud rate generator
Address 001C
16
Frequency division ratio 1/(n+1)
Transmit buffer register
Address 0018
16
Data bus
Transmit shift register
Transmit shift completion flag (TSC)
Transmit buffer empty flag (TBE)
Address 0019
16
Transmit interrupt request (TI)
UART control register
Address 001B
16
Character length selection bit
BRG count source selection bit
Transmit interrupt source selection bit
Serial I/O1 synchronous clock selection bit
Clock control circuit
Character length selection bit
7 bits
ST detector
8 bits
Serial I/O1 status register
Serial I/O1 control register
P4
0
/R
X
D
P4
2
/S
CLK1
P4
1
/T
X
D
Address 0018
16
Address 001A
16
φ
SOURCE
SP detector
ST/SP/PA generator
Note1:
φ
SOURCE indicates the followings:
X
IN
input in the frequency/2, 4, or 8 mode
On-chip oscillator divided by 4 in the on-chip oscillator mode
Sub-clock in the low-speed mode
(1)
TSC=0
TBE=1
RBF=0
TBE=0
TBE=0
RBF=1
RBF=1
ST
D
0
D
1
SP
D
0
D
1
ST
SP
TBE=1
TSC=1
ST
D
0
D
1
SP
D
0
D
1
ST
SP
Serial input RxD
Generated at 2nd bit in 2-stop-bit mode
1 start bit
1 or 0 parity bit
Notes 1
: Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit, during reception).
2
: As the transmit interrupt (TI), when either the TBE or TSC flag becomes “1”, can be selected to occur depending on the setting
of the transmit interrupt source selection bit (TIC) of the serial I/O control register.
3
: The receive interrupt (RI) is set when the RBF flag becomes “1”.
4
: After data is written to the transmit buffer when TSC flag = “1”, 0.5 to 1.5 cycles of the data shift cycle is necessary until
changing to TSC flag = “0”.
Transmit or receive clock
Transmit buffer register
write signal
Serial output TxD
Receive buffer register
read signal
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