參數資料
型號: 78Q8430-ARM9-EVM
廠商: Maxim Integrated Products
文件頁數: 18/88頁
文件大?。?/td> 0K
描述: EVALUATION MODULE 78Q8430 ARM9
產品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 1
系列: *
DS_8430_001
78Q8430 Data Sheet
Rev. 1.2
25
6
Functional Description
6.1
Internal Block Diagrams
6.1.1
Internal Digital Block
Figure 12 presents an overview of the functional layers of the 78Q8430. On the left side are the signals,
which connect to the GBI bus. On the upper and middle right, the blocks that implement the MAC side of
the MII are shown. These blocks are connected to the embedded PHY. On the lower right, connections
to the EEPROM are shown.
Bus
Control
EMI
Address
& Data
EMI
System
MAC MII
Transmit
MAC Half
Duplex
MAC
MII
Receive
MII
Register
Controller
EEPROM/
ROM
Control
Queue
Memory
Snoop
Controller
Network
Wake-up
Flow
Control
Queue
Read/Write
Logic
CAM
Packet
Classify
CTL
Controller
Memory
Manager
RMON
DMA Status
Register
TX/RX
Packet Status
Register
QUE Status
Register
MAC Status
Register
PROM_CS
PROM_CLK
PROM_DO
PROM_DI
4 Queue
Write Logic
1 Queue
Read Logic
JTAG
IEEE
1149.1
Boundary
Scan
TRSTB
TDO
TDI
TMS
TCLK
MEMWAIT
WRB/OEB
CSB
ENDIAN[1:0]
BOOTSZ[1:0]
WAITMODE
CLKMODE
BUSMODE
DATA
ADDR
PMEB
INTB
RESETB
BUSCLK
Figure 12: Internal Digital Block Diagram
6.1.2
Internal PHY
Figure 13 shows the functional blocks of the internal 78Q8430 PHY. The signals shown on the left side
are the internal MII signals to the MAC. These signals are multiplexed with their respective external pins
for use with an external PHY device. The 78Q8430 is not a two-port device. Only one PHY interface can
be operational.
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