參數(shù)資料
型號(hào)： 78Q8430-ARM9-EVM
廠商： Maxim Integrated Products
文件頁數(shù)： 79/88頁
文件大?。?/td> 0K
描述： EVALUATION MODULE 78Q8430 ARM9
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 1
系列： *
78Q8430 Data Sheet
DS_8430_001
80
Rev. 1.2
7.7.9
PHY Interrupt Control / Status Register – MR17
The Interrupt Control/Status Register provides the means for controlling and observing the events that
trigger an interrupt on the internal PHY interrupt signal. This register can also be used in a polling mode
via the MII Serial Interface as a means to observe key events within the PHY via one register address.
Bits 0 through 7 are status bits, which are each set to logic one based upon an event. These bits are
cleared after the register is read. Bits 8 through 15 of this register, when set to logic one, enable their
corresponding bit in the lower byte to signal an interrupt on the PHY interrupt signal.
Bits
Symbol
Type
Default Description
15
JABBER_IE
R/W
0
Jabber Interrupt Enable
14
RXER_IE
R/W
0
Receive Error Interrupt Enable
13
PRX_IE
R/W
0
Page Received Interrupt Enable
12
PDF_IE
R/W
0
Parallel Detect Fault Interrupt Enable
11
LP_ACK_IE
R/W
0
Link Partner Acknowledge Interrupt Enable
10
LS_CHANGE_IE
R/W
0
Link Status Change Interrupt Enable
9
RFAULT_IE
R/W
0
Remote Fault Interrupt Enable
8
ANEG-COMP_IE
R/W
0
Auto-Negotiation Complete Interrupt Enable
7
JAB_INT
RC
0
Jabber Interrupt
This bit is set high when a Jabber event is detected by
the 10Base-T circuitry.
6
RXER_INT
RC
0
Receive Error Interrupt
This bit is set high when the RX_ER signal transitions
high.
5
PRX_INT
RC
0
Page Received Interrupt
This bit is set high when a new page has been
received from the link partner during auto-negotiation.
4
PDF_INT
RC
0
Parallel Detect Fault Interrupt
This bit is set high by the auto-negotiation logic when a
parallel detect fault condition is indicated.
3
LP_ACK_INT
RC
0
Link Partner Acknowledge Interrupt
This bit is set high by the auto-negotiation logic when
FLP bursts are received with the acknowledge bit set.
2
LS_CHANGE_INT
RC
0
Link Status Change Interrupt
This bit is set when the link status transitions from an
OK status to a FAIL status, or vice versa.
1
RFAULT_INT
RC
0
Remote Fault Interrupt
This bit is set when a remote fault condition is
detected.
0
ANEG_COMP_INT
RC
0
Auto-Negotiation Complete Interrupt
This bit is set by the auto-negotiation logic upon
completion of auto-negotiation.
7.7.10 PHY Transceiver Control Register – MR19
Bit
Symbol
Type
Default Description
15:14
TXO[1:0]
R/W
01
Transmit Amplitude Selection
Sets the transmit output amplitude to account for transmit
transformer insertion loss.
00 = Gain set for 0.0dB of insertion loss
01 = Gain set for 0.4dB of insertion loss
10 = Gain set for 0.8dB of insertion loss
11 = Gain set for 1.2dB of insertion loss
13:0
RSVD
R/W
XXX
Reserved
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參數(shù)描述
78Q8430EBST#DB 功能描述:以太網(wǎng)開發(fā)工具 3-in-1 Silicon Delay Line RoHS:否 制造商:Micrel 產(chǎn)品:Evaluation Boards 類型:Ethernet Transceivers 工具用于評(píng)估:KSZ8873RLL 接口類型:RMII 工作電源電壓:
78Q8430STEM#DB 功能描述:以太網(wǎng)開發(fā)工具 3-in-1 Silicon Delay Line RoHS:否 制造商:Micrel 產(chǎn)品:Evaluation Boards 類型:Ethernet Transceivers 工具用于評(píng)估:KSZ8873RLL 接口類型:RMII 工作電源電壓:
78-R3 功能描述:3M SCOTCHCAST REENTERABLE SIGNAL 制造商:3m 系列:* 零件狀態(tài):在售 標(biāo)準(zhǔn)包裝:1
78-R4 功能描述:3M SCOTCHCAST REENTERABLE SIGNAL 制造商:3m 系列:* 零件狀態(tài):在售 標(biāo)準(zhǔn)包裝:1
78RB02 功能描述:SWITCH 2 POS DIP RECESSED UNSLD RoHS:否 類別:開關(guān) >> DIP 系列:78 特色產(chǎn)品:RDM Series Rotary DIP Switch 標(biāo)準(zhǔn)包裝:70 系列:RDM 電路:十六進(jìn)制 位置數(shù):16 觸點(diǎn)額定電壓:0.1A @ 42VDC 觸動(dòng)器類型:用于工具旋轉(zhuǎn) 觸動(dòng)器電平:凹槽式 安裝類型:通孔 方向:頂部觸動(dòng) 可清洗:是 其它名稱:EG4977-5RDMAR16PIT
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