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| 型號： | 78Q8430-ARM9-EVM |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 24/88頁 |
| 文件大?。?/td> | 0K |
| 描述： | EVALUATION MODULE 78Q8430 ARM9 |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | * |
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78Q8430 Data Sheet
DS_8430_001
30
Rev. 1.2
Snooping the contents of a frame before it is read out of the receive QUE can be useful if additional
inspection of the frame is needed, beyond what is provided by classification, to determine the disposition
of a received frame. It can also be used, in conjunction with the QUE transfer feature, to minimize host
bus overhead in responding to simple ARP or ICMP requests. In this case, the host can use the Snoop
Interface to modify a received ARP or ICMP request and convert it into the appropriate response, while
the frame is still resident in the receive QUE. The QUE Transfer feature is then used to transfer the
response directly to a TX QUE and transmit it back to the source without having to read the entire frame
into host memory.
6.5
Water Marking
The Timers module (see Section 6.8) monitors the number of free memory blocks in the system input.
There are three watermarks (Interrupt, PAUSE and Headroom), accessed via the Water Mark Values
Register (WMVR), which can be used to manage memory usage based on the size of the free memory pool.
6.5.1
Interrupt Watermark
When the number of free BLOCKs falls below the interrupt threshold, the WATER MARK interrupt in the
HIR is triggered. An interrupt threshold setting of zero disables this feature.
6.5.2
PAUSE Watermark
When the number of free BLOCKs falls below the pause threshold, the QDR bit for the PAUSE QUE
triggers the transmission of the pause frame. A pause threshold setting of zero disables this feature.
6.5.3
Headroom Watermark
When the number of free BLOCKs falls below the headroom threshold then the MAC receiver is halted
causing the MAC to drop any frames received after completion of the current frame. This condition is
cleared once the number of free BLOCKs rises back above the threshold. This prevents a saturated
receiver from consuming all free memory thereby locking out the local transmitter. A headroom setting of
zero disables this feature.
6.6
Counters
A block of hardware counters is implemented to allow monitoring transmit and receive statistics. These
counters are accessed and managed by using the Count Data Register (CDR), the Counter Control
6.6.1
Summary of Counters
Table 23 provides a summary of all counters by address. Counters at addresses 0x00 through 0x0E are
transmit counters. Counters at addresses 0x0F through 0x27 are receive counters.
Table 23: Counter Summary
Counter
Address
Counter Description
0x00
Transmitted Packets, 0 Collisions, not deferred or excessive deferred
0x01
Transmitted Packets, 1 Collision
0x02
Transmitted Packets, 2-15 Collisions
0x03
Excessive Collisions
0x04
Deferred transmissions
0x05
Late Collisions
0x06
MAC errors (TX under-run or transmit halted)
0x07
Lost carrier sense errors
0x08
Excessive deferrals
0x09
Total packets transmitted
0x0A
Multicast packets
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