參數(shù)資料
型號(hào): 78Q8430-ARM9-EVM
廠(chǎng)商: Maxim Integrated Products
文件頁(yè)數(shù): 52/88頁(yè)
文件大?。?/td> 0K
描述: EVALUATION MODULE 78Q8430 ARM9
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 1
系列: *
78Q8430 Data Sheet
DS_8430_001
56
Rev. 1.2
7.5
QUE Registers
7.5.1
Packet Control Word Register
Name: PCWR
Reset Val: 0x0000_0000
Block: QUE
Address: 0x000
Bits
Type
Default
Description
31:30
X
Reserved
29:25
WO
N/A
Preload
The number of bytes to pre-load into the MAC TX FIFO before the
frame begins transmission to the PHY. This may need to be non-zero
for large IP headers that want to have the checksum inserted to ensure
the checksum is not transmitted before the end of the header is loaded.
24:16
WO
N/A
Packet ID
The 9-bit ID value used to identify this packet in the TX status FIFO.
15:10
WO
N/A
IP Header Offset
Offset in bytes to the IP header in this frame. If this value is non-zero
then the IP header checksum will be corrected.
9
WO
N/A
Append CRC
When set, the transmitter shall append the correct CRC checksum to
the end of the frame.
8
WO
N/A
Fix CRC
When set, the transmitter shall correct the existing CRC checksum on
the end of the packet.
7
X
Reserved
6
WO
N/A
Disable Padding
For small packets (<64 Bytes).
5
WO
N/A
Late Notify
Interrupt on completion.
4
WO
N/A
Early Notify
Interrupt at beginning of transmission.
3
WO
N/A
Interrupt on excessive collisions.
2
WO
N/A
Disable deferral timeout.
1
WO
N/A
Enable fast back-off timer.
0
X
Reserved
7.5.2
Packet Size Register
Name: PSZR
Reset Val: 0x0000_0000
Block: QUE
Address: 0x004
Bits
Type
Default
Description
31:16
X
Reserved
15:0
RW
0000
Packet Size
The size, in bytes, of the packet that will be added to the QUE.
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