參數(shù)資料
型號(hào)： 78Q8430-ARM9-EVM
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 53/88頁(yè)
文件大小： 0K
描述： EVALUATION MODULE 78Q8430 ARM9
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 1
系列： *
DS_8430_001
78Q8430 Data Sheet
Rev. 1.2
57
7.5.3
Setup Transmit Data Register
Name: STDR
Reset Val: 0x0000_0000
Block: QUE
Address: 0x008
Bits
Type
Default
Description
31:25
X
Reserved
24
RW
Endian
The network transmit byte order.
Set = big endian (Most significant byte transmit first)
Clear = little endian (Least significant byte transmit first)
23:20
X
Reserved
19:18
RW
00
Start Offset
The number of bytes to ignore on the first data word written for this
buffer. This byte mask is applied any time the Count value is
non-zero. After each time it is applied, however, it is reset to zero such
that it is really only applied on the first write.
17:16
RW
00
End Offset
The number of bytes to ignore on the last data word written for this
buffer. This byte mask is applied any time the Count value is zero.
Unlike the Start Offset, the End Offset is not self clearing. This means
that the End Offset will be applied to all writes to the QUE once the
Count value reaches zero, unless the host clears the End Offset. The
remainder of PSZR will override the End Offset when a write occurs
and the PSZR value is less than four.
15:14
X
Reserved
13:0
RW
0000
Count
The total number of writes needed to complete the buffer minus one.
This counter decrements on each write operation to the QUE. This
counter decrements on each write operation to the QUE until it reaches
zero. The Count value will remain zero until the next host write. The
value written here must be one less than the number of writes in the
buffer so that the Count value will equal zero on the last write and
cause the End Offset to be applied.
Note: The PCWR and PSZR must be set before writing to the STDR.
7.5.4
Transmit Data Register
Name: TDR
Reset Val: 0x0000_0000
Block: QUE
Address: 0x00C
Bits
Type
Default
Description
31:0
WO
N/A
Packet Data to Add to the QUE
Data written to this register is added to the QUE to which the register
belongs.
7.5.5
Receive Data Register
Name: RDR
Reset Val: 0x0000_0000
Block: QUE
Address: 0x010
Bits
Type
Default
Description
1:0
RO
N/A
Packet Data Read from the QUE
Data read from this register is shifted out of the QUE to which the
register belongs. The RPSR should be consulted to make sure data is
available before reading this register.
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78Q8430EBST#DB 功能描述:以太網(wǎng)開(kāi)發(fā)工具 3-in-1 Silicon Delay Line RoHS:否 制造商:Micrel 產(chǎn)品:Evaluation Boards 類型:Ethernet Transceivers 工具用于評(píng)估:KSZ8873RLL 接口類型:RMII 工作電源電壓:
78Q8430STEM#DB 功能描述:以太網(wǎng)開(kāi)發(fā)工具 3-in-1 Silicon Delay Line RoHS:否 制造商:Micrel 產(chǎn)品:Evaluation Boards 類型:Ethernet Transceivers 工具用于評(píng)估:KSZ8873RLL 接口類型:RMII 工作電源電壓:
78-R3 功能描述:3M SCOTCHCAST REENTERABLE SIGNAL 制造商:3m 系列:* 零件狀態(tài):在售 標(biāo)準(zhǔn)包裝:1
78-R4 功能描述:3M SCOTCHCAST REENTERABLE SIGNAL 制造商:3m 系列:* 零件狀態(tài):在售 標(biāo)準(zhǔn)包裝:1
78RB02 功能描述:SWITCH 2 POS DIP RECESSED UNSLD RoHS:否 類別:開(kāi)關(guān) >> DIP 系列:78 特色產(chǎn)品:RDM Series Rotary DIP Switch 標(biāo)準(zhǔn)包裝:70 系列:RDM 電路:十六進(jìn)制 位置數(shù):16 觸點(diǎn)額定電壓:0.1A @ 42VDC 觸動(dòng)器類型:用于工具旋轉(zhuǎn) 觸動(dòng)器電平:凹槽式 安裝類型:通孔 方向:頂部觸動(dòng) 可清洗:是 其它名稱:EG4977-5RDMAR16PIT
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