參數(shù)資料
型號(hào): 78Q8430-ARM9-EVM
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 68/88頁(yè)
文件大?。?/td> 0K
描述: EVALUATION MODULE 78Q8430 ARM9
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 1
系列: *
78Q8430 Data Sheet
DS_8430_001
70
Rev. 1.2
Name: RCR
Reset Val: 0x0000_0002
Block: CTL
Address: 0x1A8
Bits
Type
Default
Description
1:0
RW
10
Match Control
How to generate a CAM reference word for the next pass. Match control
is described in detail in Table 27.
00 = DONE
10 = MD
01 = MX
11 = DROP
7.6.33 Que Status Interrupt Register
Name: QSIR
Reset Val: 0x0000_0000
Block: CTL
Address: 0x1C0
Bits
Type
Default
Description
31
RO
QDR Rise
Rising edge detected on QUE 7 QDR bit.
30
RO
QDR Fall
Falling edge detected on QUE 7 QDR bit.
29
RO
A Rise
Rising edge detected on QUE 7 QSR A bit. (See QSR)
28
RO
B Rise
Rising edge detected on QUE 7 QSR B bit. (See QSR)
27:24
RO
QUE 6
QDR Rise, QDR Fall, A Rise and B Rise interrupt bits for QUE 6.
23:20
RO
QUE 5
QDR Rise, QDR Fall, A Rise and B Rise interrupt bits for QUE 5.
19:16
RO
QUE 4
QDR Rise, QDR Fall, A Rise and B Rise interrupt bits for QUE 4.
15:12
RO
QUE 3
QDR Rise, QDR Fall, A Rise and B Rise interrupt bits for QUE 3.
11:8
RO
QUE 2
QDR Rise, QDR Fall, A Rise and B Rise interrupt bits for QUE 2.
7:4
RO
QUE 1
QDR Rise, QDR Fall, A Rise and B Rise interrupt bits for QUE 1.
3:0
RO
QUE 0
QDR Rise, QDR Fall, A Rise and B Rise interrupt bits for QUE 0.
Note: All bits are cleared on read.
7.6.34 Que Status Mask Register
Name: QSMR
Reset Val: 0x0000_0000
Block: CTL
Address: 0x1C4
Bits
Type
Default
Description
31:0
RW
QUE Status Interrupt Mask
When a bit is set it enables the QUE status interrupt for the
corresponding bit in the QSIR. When a bit is clear, the corresponding
bit in the QSIR will still be set on its event and cleared on read but will
not be passed on to the HIR.
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