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參數(shù)資料
| 型號(hào)： | 80546KF |
| 廠商： | Intel Corp. |
| 英文描述： | 64-bit Intel Xeon Processor MP with up to 8MB L3 Cache |
| 中文描述： | 64位Intel Xeon處理器MP的高達(dá)8MB三級(jí)高速緩存 |
| 文件頁數(shù)： | 106/138頁 |
| 文件大?。?/td> | 2666K |
| 代理商： | 80546KF |
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106
64-bit Intel
Xeon Processor MP with up to 8MB L3 Cache Datasheet
Features
processor enters the Stop-Grant state, issuing a Stop-Grant Special Bus Cycle (SBC) for each
processor or logical processor. The chipset needs to account for a variable number of processors
asserting the Stop-Grant SBC on the bus before allowing the processor to be transitioned into one
of the lower processor power states. Refer to the applicable chipset specification for more
information.
8.2.1
Normal State
This is the normal operating state for the processor.
8.2.2
HALT or Enhanced Power Down State
The Enhanced HALT power down state is configured and enabled via the BIOS. If the Enhanced
HALT state is not enabled, the default power down state entered will be HALT. Refer to the section
below for details on HALT and Enhanced HALT states.
8.2.2.1
HALT Power Down State
HALT is a low power state entered when all logical processors have executed the HALT or
MWAIT instruction. When one of the logical processors executes the HALT or MWAIT
instruction, that logical processor is halted; however, the other processor continues normal
operation. The processor transitions to the Normal state upon the occurrence of SMI#, BINIT#,
INIT#, LINT[1:0] (NMI, INTR), or an interrupt delivered over the front side bus. RESET# causes
the processor to immediately initialize itself.
The return from a System Management Interrupt (SMI) handler can be to either Normal Mode or
the HALT Power Down state. See the
IA-32 Intel
Architecture Software Developer's Manual,
Volume 3: System Programming Guide
for more information.
The system can generate a STPCLK# while the processor is in the HALT Power Down state. When
the system deasserts the STPCLK# interrupt, the processor returns execution to the HALT state.
While in HALT Power Down state, the processor processes bus snoops and interrupts.
8.2.2.2
Enhanced HALT Power Down State
Enhanced HALT state is a low power state entered when all logical processors have executed the
HALT or MWAIT instructions and Enhanced HALT state has been enabled via the BIOS. When
one of the logical processors executes the HALT instruction, that logical processor is halted;
however, the other processor continues normal operation. The Enhanced HALT state is generally a
lower power state than the Stop Grant state.
The processor automatically transitions to a lower core frequency and voltage operating point
before entering the Enhanced HALT state. Note that the processor FSB frequency is not altered;
only the internal core frequency is changed. When entering the low power state, the processor first
switches to the lower bus ratio and then transitions to the lower VID.
While in the Enhanced HALT state, the processor processes bus snoops.
The processor exits the Enhanced HALT state when a break event occurs. When the processor exits
the Enhanced HALT state, it first transitions the VID to the original value and then changes the bus
ratio back to the original value.
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