參數(shù)資料
型號(hào)： 80546KF
廠商： Intel Corp.
英文描述： 64-bit Intel Xeon Processor MP with up to 8MB L3 Cache
中文描述： 64位Intel Xeon處理器MP的高達(dá)8MB三級(jí)高速緩存
文件頁(yè)數(shù)： 42/138頁(yè)
文件大小： 2666K
代理商： 80546KF
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42
64-bit Intel
Xeon Processor MP with up to 8MB L3 Cache Datasheet
Electrical Specifications
NOTES:
1. These parameters are based on design characterization and are not tested.
2. All AC timings for the SMBus signals are referenced at V
IL_MAX
or V
IL_MIN
and measured at the processor
pins. Refer to
Figure 2-16
.
3. Minimum time allowed between request cycles.
4. Rise time is measured from (V
IL_MAX
- 0.15V) to (V
IH_MIN
+ 0.15V). Fall time is measured from
(0.9 * SM_VCC) to (V
IL_MAX
- 0.15V). DC parameters are specified in
Table 2-18
.
5. Following a write transaction, an internal write cycle time of 10ms must be allowed before starting the next
transaction
2.13
Processor AC Timing Waveforms
The following figures are used in conjunction with the AC timing tables (
Table 2-21
through
Table 2-28
).
Note:
For
Figure 2-7
through
Figure 2-19
, the following apply:
1. All common clock AC timings for AGTL+ signals are referenced to the Crossing Voltage
(V
) of the BCLK[1:0] at rising edge of BCLK0. All common clock AGTL+ signal
timings are referenced at GTLREF at the processor core.
2. All source synchronous AC timings for AGTL+ signals are referenced to their associated
strobe (address or data) at GTLREF. Source synchronous data signals are referenced to the
falling edge of their associated data strobe. Source synchronous address signals are referenced
to the rising and falling edge of their associated address strobe. All source synchronous
AGTL+ signal timings are referenced at GTLREF at the processor silicon.
3. All AC timings for AGTL+ strobe signals are referenced to BCLK[1:0] at V
CROSS
. All AGTL+
strobe signal timings are referenced at GTLREF at the processor silicon.
4. All AC timings for the TAP signals are referenced to the TCK at 0.5 * V
TT
at the processor
pins. All TAP signal timings (TMS, TDI, etc.) are referenced at 0.5 * V
TT
at the processor
pins.
5. All AC timings for the SMBus signals are referenced to the SM_CLK at 0.5 * SM_VCC
at the
processor pins. All SMBus signal timings (SM_DAT, SM_CLK, etc.) are referenced at
V
IL_MAX
or V
IL_MIN
at the processor pins.
Figure 2-6. Electrical Test Circuit
V
TT
45 ohms, 156 ps/in, 550 mils
L = 2.4nH
C = 1.2pF
V
TT
R
LOAD
= 50 ohms
AC Timings specified at this point
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