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| 型號(hào)： | 80546KF |
| 廠商： | Intel Corp. |
| 英文描述： | 64-bit Intel Xeon Processor MP with up to 8MB L3 Cache |
| 中文描述： | 64位Intel Xeon處理器MP的高達(dá)8MB三級(jí)高速緩存 |
| 文件頁(yè)數(shù)： | 92/138頁(yè) |
| 文件大?。?/td> | 2666K |
| 代理商： | 80546KF |
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92
64-bit Intel
Xeon Processor MP with up to 8MB L3 Cache Datasheet
Signal Definitions
MCERR#
I/O
MCERR# (Machine Check Error) is asserted to indicate an unrecoverable error
or a bus protocol violation. It may be driven by all processor front side bus
agents.
MCERR# assertion conditions are configurable at a system level. Assertion
options are defined as follows:
Enabled or disabled.
Asserted, if configured, for internal errors along with IERR#.
Asserted, if configured, by the request initiator of a bus transaction after it
observes an error.
Asserted by any bus agent when it observes an error in a bus transaction.
For more details regarding machine check architecture, refer to the
IA-32 Intel
Software Developer’s Manual, Volume 3: System Programming Guide
.
Since multiple agents may drive this signal at the same time, MCERR# is a
wired-OR signal which must connect the appropriate pins of all processor front
side bus agents. In order to avoid wire-OR glitches associated with
simultaneous edge transitions driven by multiple drivers, MCERR# is activated
on specific clock edges and sampled on specific clock edges.
ODTEN
I
ODTEN (On-die termination enable) should be connected to V
through a
resistor to enable on-die termination for end bus agents. For middle bus
agents, pull this signal down via a resistor to ground to disable on-die
termination. Whenever ODTEN is high, on-die termination will be active,
regardless of other states of the bus.
OOD#
I
OOD# allows data delivery to occur subsequent to IDS# assertion during the
Deferred Phase.
PROCHOT#
O
The assertion of PROCHOT# (processor hot) indicates that the processor die
temperature has reached its thermal limit. See
Section 7.2.4
for more details.
PWRGOOD
I
PWRGOOD (Power Good) is an input. The processor requires this signal to be
a clean indication that all processor clocks and power supplies are stable and
within their specifications. “Clean” implies that the signal will remain low
(capable of sinking leakage current), without glitches, from the time that the
power supplies are turned on until they come within specification. The signal
must then transition monotonically to a high state.
Figure 2-18
illustrates the
relationship of PWRGOOD to the RESET# signal. PWRGOOD can be driven
inactive at any time, but clocks and power must again be stable before a
subsequent rising edge of PWRGOOD. It must also meet the minimum pulse
width specification in
Table 2-21
, and be followed by a 1 ms active RESET#
pulse.
The PWRGOOD signal must be supplied to the processor. This signal is used
to protect internal circuits against voltage sequencing issues. It should be
driven high throughout boundary scan operation.
REQ[4:0]#
I/O
REQ[4:0]# (Request Command) must connect the appropriate pins of all
processor front side bus agents. They are asserted by the current bus owner to
define the currently active transaction type. These signals are source
synchronous to ADSTB[1:0]#. Refer to the AP[1:0]# signal description for
details on parity checking of these signals.
RESET#
I
Asserting the RESET# signal resets all processors to known states and
invalidates their internal caches without writing back any of their contents. For a
power-on Reset, RESET# must stay active for at least 1 ms after V
CC
and
BCLK have reached their specified levels. On observing active RESET#, all
front side bus agents will deassert their outputs within two clocks. RESET#
must not be kept asserted for more than 10 ms.
A number of bus signals are sampled at the active-to-inactive transition of
RESET# for power-on configuration. These configuration options are described
in
Section 8.1
.
Table 6-1. Signal Definitions (Sheet 6 of 9)
Name
Type
Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 8085AH | 8 BIT HMOS MICROPROCESSORS |
| 8085AH-1 | 8 BIT HMOS MICROPROCESSORS |
| 8085AH-2 | 8 BIT HMOS MICROPROCESSORS |
| 8087 | MATH COPROCESSOR |
| 8087-1 | Circular Connector; MIL SPEC:MIL-DTL-38999 Series III; Body Material:Metal; Series:TV06; No. of Contacts:61; Connector Shell Size:25; Connecting Termination:Crimp; Circular Shell Style:Straight Plug; Body Style:Straight |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 80546KG3200FA | 制造商:undefined 功能描述: |
| 805470 | 制造商:Phoenix Contact 功能描述:Labels Individual Label Polyester White 8x20mm |
| 80-5470-001 | 制造商:Applied Engineering Products (AEP) 功能描述:13"CBL W/CON ON BOTH ENDS - PLUG, R/A PUSHON - Bulk |
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