參數(shù)資料
型號(hào)： 80546KF
廠商： Intel Corp.
英文描述： 64-bit Intel Xeon Processor MP with up to 8MB L3 Cache
中文描述： 64位Intel Xeon處理器MP的高達(dá)8MB三級(jí)高速緩存
文件頁數(shù)： 20/138頁
文件大小： 2666K
代理商： 80546KF
20
64-bit Intel
Xeon Processor MP with up to 8MB L3 Cache Datasheet
Electrical Specifications
NOTES:
1. Diagram not to scale.
2. No specification for frequencies beyond f
(core frequency).
3. f
peak
, if existent, should be less than 0.05MHz.
4. f
core
represents the maximum core frequency supported by the platform.
2.2
Voltage Identification (VID)
The VID[5:0] pins supply the encodings that determine the voltage to be supplied by the V
CC
(the
core voltage for the processor) voltage regulator. The VID specification for the processor is defined
by the
Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 10.1
Design Guidelines
, the
Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down
(EVRD) 10.2 Design Guidelines
, and the
Voltage Regulator Module (VRM) 10.2L Design
Guidelines.
Please refer to these documents for all VRM and VRD design issues. The voltage set
by the VID signals is the maximum V
CC
voltage allowed by the processor. VID signals are open
drain outputs, which must be pulled up to V
TT
. Please refer to
Table 2-13
for the DC specifications
for these signals. A minimum V
CC
voltage is provided in
Table 2-9
and changes with frequency.
This allows processors running at a higher frequency to have a relaxed minimum V
CC
voltage
specification. The specifications have been set such that one voltage regulator can work with all
supported frequencies.
Figure 2-2. Phase Lock Loop (PLL) Filter Requirements
0 dB
-28 dB
-34 dB
0.2 dB
forbidden
zone
-0.5 dB
forbidden
zone
1 MHz
66 MHz
fcore
fpeak
1 Hz
DC
passband
high frequency
band
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