參數(shù)資料
型號： 80546KF
廠商： Intel Corp.
英文描述： 64-bit Intel Xeon Processor MP with up to 8MB L3 Cache
中文描述： 64位Intel Xeon處理器MP的高達8MB三級高速緩存
文件頁數(shù)： 114/138頁
文件大?。?/td> 2666K
代理商： 80546KF
114
64-bit Intel
Xeon Processor MP with up to 8MB L3 Cache Datasheet
Features
The SMBus thermal sensor feature in the processor cannot be used to measure T
CASE
. The T
CASE
specification in
Section 7
must be met regardless of the reading of the processor's thermal sensor in
order to ensure adequate cooling for the entire processor. The SMBus thermal sensor feature is only
available while V
CC
and SM_VCC are at valid levels and the processor is not in a low-power state.
8.4.5
Thermal Sensor Supported SMBus Transactions
The thermal sensor responds to five of the SMBus packet types: Write Byte, Read Byte, Send Byte,
Receive Byte, and Alert Response Address (ARA). The Send Byte packet can be used for sending
one-shot commands. The Receive Byte packet accesses the register commanded by the last Read
Byte packet and can be used to continuously read from a register. If a Receive Byte packet was
preceded by a Write Byte or send Byte packet more recently than a Read Byte packet, then the
behavior is undefined.
Table 8-5
through
Table 8-9
diagram the five packet types. In these figures,
‘S’ represents the SMBus start bit, ‘P’ represents a stop bit, ‘Ack’ represents an acknowledge, and
‘///’ represents a negative acknowledge (NACK). The shaded bits are transmitted by the thermal
sensor, and the bits that aren’t shaded are transmitted by the SMBus host controller.
Table 8-10
shows the encoding of the command byte.
NOTE:
1. This is an 8-bit field. The device which sent the alert will respond to the ARA Packet with its address in the
seven most significant bits. The least significant bit is undefined and may return as a ‘1’ or ‘0’. See
Section 8.4.8
for details on the Thermal Sensor Device addressing.
Table 8-5. Write Byte SMBus Packet
S
Slave Address
Write
Ack
Command Code
Ack
Data
Ack
P
1
7-bits
0
1
8-bits
1
8-bits
1
1
Table 8-6. Read Byte SMBus Packet
S
Slave
Address
Write
Ack
Command
Code
Ack
S
Slave
Address
Read
Ack
Data
///
P
1
7-bits
0
1
8-bits
1
1
7-bits
1
1
8-
bits
1
1
Table 8-7. Send Byte SMBus Packet
S
Slave Address
Write
Ack
Command Code
Ack
P
1
7-bits
0
1
8-bits
1
1
Table 8-8. Receive Byte SMBus Packet
S
Slave Address
Read
Ack
Data
///
P
1
7-bits
1
1
8-bits
1
1
Table 8-9. ARA SMBus Packet
S
ARA
Read
Ack
Address
///
P
1
0001 100
1
1
Device Address
1
1
1
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