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參數(shù)資料
| 型號(hào)： | 80546KF |
| 廠商： | Intel Corp. |
| 英文描述： | 64-bit Intel Xeon Processor MP with up to 8MB L3 Cache |
| 中文描述： | 64位Intel Xeon處理器MP的高達(dá)8MB三級(jí)高速緩存 |
| 文件頁(yè)數(shù)： | 90/138頁(yè) |
| 文件大?。?/td> | 2666K |
| 代理商： | 80546KF |
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90
64-bit Intel
Xeon Processor MP with up to 8MB L3 Cache Datasheet
Signal Definitions
DBSY#
I/O
DBSY# (Data Bus Busy) is asserted by the agent responsible for driving data
on the processor front side bus to indicate that the data bus is in use. The data
bus is released after DBSY# is deasserted. This signal must connect the
appropriate pins on all processor front side bus agents.
DEFER#
I
DEFER# is asserted by an agent to indicate that a transaction cannot be
guaranteed in-order completion. Assertion of DEFER# is normally the
responsibility of the addressed memory or I/O agent. This signal must connect
the appropriate pins of all processor front side bus agents.
DEP[7:0]#
I/O
The DEP[7:0]# (data bus ECC protection) signals provide optional ECC
protection for the data bus. They are driven by the agent responsible for driving
D[63:0]#, and, if ECC is implemented, must connect the appropriate pins of all
bus agents which use them.
Furthermore, the DBI# pins determine the polarity of the ECC signals. Each
pair of 2 ECC signals corresponds to one DBI# signal. When the DBI# signal is
active, the corresponding ECC pair is inverted and therefore sampled active
high.
DP[3:0]#
I/O
DP[3:0]# (Data Parity) provide optional parity protection for the data bus. They
are driven by the agent responsible for driving D[63:0]#, and, if parity is
implemented, must connect the appropriate pins of all bus agents which use
them.
DRDY#
I/O
DRDY# (Data Ready) is asserted by the data driver on each data transfer,
indicating valid data on the data bus. In a multi-common clock data transfer,
DRDY# may be deasserted to insert idle clocks. This signal must connect the
appropriate pins of all processor front side bus agents.
DSTBN[3:0]#
I/O
Data strobe used to latch in D[63:0]#, DEP[7:0]# and DBI[3:0]#.
DSTBP[3:0]#
I/O
Data strobe used to latch in D[63:0]#, DEP[7:0]# and DBI[3:0]#.
FERR#/PBE#
O
FERR#/PBE# (floating-point error/pending break event) is a multiplexed signal
and its meaning is qualified by STPCLK#. When STPCLK# is not asserted,
FERR#/PBE# indicates a floating-point error and will be asserted when the
processor detects an unmasked floating-point error. When STPCLK# is not
asserted, FERR#/PBE# is similar to the ERROR# signal on the Intel 387
coprocessor, and is included for compatibility with systems using MS-DOS*-
type floating-point error reporting. When STPCLK# is asserted, an assertion of
FERR#/PBE# indicates that the processor has a pending break event waiting
for service. The assertion of FERR#/PBE# indicates that the processor should
be returned to the Normal state. For additional information on the pending
break event functionality, including the identification of support of the feature
and enable/disable information, refer to Volume 3 of the
IA-32 Intel
Architecture Software Developer’s Manual
and the
AP-485
Intel Processor
Identification and the CPUID Instruction
application note.
FORCEPR#
I
This input can be used to force activation of the Thermal Control Circuit.
GTLREF[3:0]
I
GTLREF determines the signal reference level for AGTL+ input pins. GTLREF
is used by the AGTL+ receivers to determine if a signal is an electrical 0 or an
electrical 1. Please refer to
Table 2-19
for further details.
HIT#
HITM#
I/O
I/O
HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction snoop operation
results. Any front side bus agent may assert both HIT# and HITM# together to
indicate that it requires a snoop stall, which can be continued by reasserting
HIT# and HITM# together, every other common clock.
Since multiple agents may deliver snoop results at the same time, HIT# and
HITM# are wire-OR signals which must connect the appropriate pins of all
processor front side bus agents. In order to avoid wire-OR glitches associated
with simultaneous edge transitions driven by multiple drivers, HIT# and HITM#
are activated on specific clock edges and sampled on specific clock edges.
Table 6-1. Signal Definitions (Sheet 4 of 9)
Name
Type
Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 8085AH | 8 BIT HMOS MICROPROCESSORS |
| 8085AH-1 | 8 BIT HMOS MICROPROCESSORS |
| 8085AH-2 | 8 BIT HMOS MICROPROCESSORS |
| 8087 | MATH COPROCESSOR |
| 8087-1 | Circular Connector; MIL SPEC:MIL-DTL-38999 Series III; Body Material:Metal; Series:TV06; No. of Contacts:61; Connector Shell Size:25; Connecting Termination:Crimp; Circular Shell Style:Straight Plug; Body Style:Straight |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 80546KG3200FA | 制造商:undefined 功能描述: |
| 805470 | 制造商:Phoenix Contact 功能描述:Labels Individual Label Polyester White 8x20mm |
| 80-5470-001 | 制造商:Applied Engineering Products (AEP) 功能描述:13"CBL W/CON ON BOTH ENDS - PLUG, R/A PUSHON - Bulk |
| 80547001 | 功能描述:MOTOR 82540 250RPM 220-230V 50/6 制造商:crouzet 系列:* 零件狀態(tài):在售 標(biāo)準(zhǔn)包裝:6 |
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