參數(shù)資料
型號(hào): 80546KF
廠商: Intel Corp.
英文描述: 64-bit Intel Xeon Processor MP with up to 8MB L3 Cache
中文描述: 64位Intel Xeon處理器MP的高達(dá)8MB三級(jí)高速緩存
文件頁數(shù): 95/138頁
文件大?。?/td> 2666K
代理商: 80546KF
64-bit Intel
Xeon Processor MP with up to 8MB L3 Cache Datasheet
95
Signal Definitions
§
V
CCA
I
V
provides isolated power for the analog portion of the internal PLL’s. Use a
discrete RLC filter to provide clean power.
V
CCA_CACHE
I
V
provides isolated power for the L3 cache PLL. Use a discrete RLC
filter to provide clean power.
V
CC_CACHE_SENSE
V
SS_CACHE_SENSE
O
V
and V
provide isolated, low impedance
connections to the processor cache voltage (V
) and ground (V
). They
can be used to sense or measure voltage or ground near the silicon with little
noise.
V
CCIOPLL
I
V
CCIOPLL
provides isolated power for digital portion of the internal PLL’s.
The on-die PLL filter solution will not be implemented on this platform. The
V
CCPLL
input should be left unconnected.
V
CCPLL
I
V
CCSENSE
V
SSSENSE
O
V
CCSENSE
and V
SSSENSE
provide isolated, low impedance connections to the
processor core voltage (V
) and ground (V
). These signals must be con-
nected to the voltage regulator feedback signals, which ensure the output volt-
age (i.e. processor voltage) remains within specification.
VID[5:0]
O
VID[5:0] (Voltage ID) pins are used to support automatic selection of V
.
These are open drain signals that are driven by the processor and must be
pulled to no more than 3.3 V (+5% tolerance) with a resistor. Conversely, the
V
VR output must be disabled prior to the voltage supply for these pins
becoming invalid. The VID pins are needed to support processor voltage
specification variations. See
Table 2-3
for definitions of these pins. The V
CC
VR
must supply the voltage that is requested by these pins, or disable itself.
VIDPWRGD
I
The processor requires this input to determine that the supply voltage for
BSEL[1:0], VID[5:0], and CVID[3:0] is stable and within specification.
V
SS
I
V
SS
is the ground plane for the processor.
V
provides an isolated,
internal
ground for internal PLL’s. Do not connect
directly to ground. This pin is to be connected to V
CCA
and V
CCIOPLL
through a
discrete filter circuit.
V
SSA
I
V
SSA_CACHE
I
V
provides an isolated,
internal
ground for the L3 cache PLL. Do
not connect directly to ground.
V
TT
I
V
TT
is the front side bus termination voltage.
VTTEN can be used as an output enable for the V
regulator. VTTEN is used
as an electrical key to prevent processors with mechanically-equivalent pinouts
from accidentally booting in a 64-bit Intel
Xeon processor MP with up to
8MB L3 cache platform. Since VTTEN is an open circuit on the processor
package, VTTEN must be pulled up on the motherboard.
VTTEN
O
Table 6-1. Signal Definitions (Sheet 9 of 9)
Name
Type
Description
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