參數(shù)資料
型號： 80546KF
廠商： Intel Corp.
英文描述： 64-bit Intel Xeon Processor MP with up to 8MB L3 Cache
中文描述： 64位Intel Xeon處理器MP的高達8MB三級高速緩存
文件頁數(shù)： 25/138頁
文件大小： 2666K
代理商： 80546KF
64-bit Intel
Xeon Processor MP with up to 8MB L3 Cache Datasheet
25
Electrical Specifications
2.6
Front Side Bus Signal Groups
The front side bus signals are grouped by buffer type as listed in
Table 2-5
. The buffer type
indicates which AC and DC specifications apply to the signals. AGTL+ input signals have
differential input buffers that use GTLREF as a reference level. In this document, the term “AGTL+
Input” refers to the AGTL+ input group as well as the AGTL+ I/O group when receiving. Similarly,
“AGTL+ Output” refers to the AGTL+ output group as well as the AGTL+ I/O group when driving.
AGTL+ asynchronous outputs can become active anytime and include an active pMOS pull-up
transistor to assist during the first clock of a low-to-high voltage transition.
Implementing a source synchronous data bus requires specifying two sets of timing parameters.
One set is for common clock signals which are dependent upon the rising edge of BCLK0 (ADS#,
HIT#, HITM#, etc.). The second set is for the source synchronous signals that are relative to their
respective strobe lines (data and address) as well as the rising edge of BCLK0. Asynchronous
signals are present (A20M#, IGNNE#, etc.) and can become active at any time during the clock
cycle.
Table 2-5
identifies signals as common clock, source synchronous, and asynchronous.
Table 2-5. Front Side Bus Pin Groups (Sheet 1 of 2)
Signal Group
Type
Signals
1
AGTL+ Common Clock Input
Synchronous to BCLK[1:0]
BPRI#, BR[3:1]#, DEFER#, ID[7:0]#, IDS#,
OOD#, RESET#, RS[2:0]#, RSP#, TRDY#
AGTL+ Common Clock I/O
Synchronous to BCLK[1:0]
ADS#, AP[1:0]#, BINIT#, BNR#, BPM[5:0]#,
BR0#, DBSY#, DP[3:0]#, DRDY#, HIT#,
HITM#, LOCK#, MCERR#
AGTL+ Source Synchronous
I/O
Synchronous to associated
strobe
AGTL+ Strobe Input/Output
Synchronous to BCLK[1:0]
ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]#
AGTL+ Asynchronous Output
Asynchronous
FERR#/PBE#, IERR#, PROCHOT#
GTL+ Asynchronous Input
Asynchronous
A20M#, FORCEPR#, IGNNE#, INIT#, LINT0/
INTR, LINT1/NMI, SMI#, STPCLK#
GTL+ Asynchronous Output
Asynchronous
THERMTRIP#
TAP Input
Synchronous to TCK
TCK, TDI, TMS
TAP Input
Asynchronous
TRST#
TAP Output
Synchronous to TCK
TDO
Signals
Associated Strobe
REQ[4:0]#,
A[37:36,16:3]#
ADSTB0#
A[39:38,35:17]#
ADSTB1#
D[15:0]#, DEP[1:0]#,
DBI0#
DSTBP0#, DSTBN0#
D[31:16]#, DEP[3:2]#,
DBI1#
DSTBP1#, DSTBN1#
D[47:32]#, DEP[5:4]#,
DBI2#
DSTBP2#, DSTBN2#
D[63:48]#, DEP[7:6]#,
DBI3#
DSTBP3#, DSTBN3#
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