![](http://datasheet.mmic.net.cn/340000/80546KF_datasheet_16452109/80546KF_71.png)
64-bit Intel
Xeon Processor MP with up to 8MB L3 Cache Datasheet
71
Pin Listing
D55#
AB10
Source Sync
Input/Output
D56#
AC8
Source Sync
Input/Output
D57#
AD7
Source Sync
Input/Output
D58#
AE7
Source Sync
Input/Output
D59#
AC6
Source Sync
Input/Output
D60#
AC5
Source Sync
Input/Output
D61#
AA8
Source Sync
Input/Output
D62#
Y9
Source Sync
Input/Output
D63#
AB6
Source Sync
Input/Output
DBI0#
AC27
Source Sync
Input/Output
DBI1#
AD22
Source Sync
Input/Output
DBI2#
AE12
Source Sync
Input/Output
DBI3#
AB9
Source Sync
Input/Output
DBSY#
F18
Common Clk
Input/Output
DEFER#
C23
Common Clk
Input
DEP0#
AD31
Source Sync
Input/Output
DEP1#
AD30
Source Sync
Input/Output
DEP2#
AE16
Source Sync
Input/Output
DEP3#
AE15
Source Sync
Input/Output
DEP4#
AE8
Source Sync
Input/Output
DEP5#
AD6
Source Sync
Input/Output
DEP6#
AC4
Source Sync
Input/Output
DEP7#
AA4
Source Sync
Input/Output
DP0#
AC18
Common Clk
Input/Output
DP1#
AE19
Common Clk
Input/Output
DP2#
AC15
Common Clk
Input/Output
DP3#
AE17
Common Clk
Input/Output
DRDY#
E18
Common Clk
Input/Output
DSTBN0#
Y21
Source Sync
Input/Output
DSTBN1#
Y18
Source Sync
Input/Output
DSTBN2#
Y15
Source Sync
Input/Output
DSTBN3#
Y12
Source Sync
Input/Output
DSTBP0#
Y20
Source Sync
Input/Output
DSTBP1#
Y17
Source Sync
Input/Output
DSTBP2#
Y14
Source Sync
Input/Output
DSTBP3#
Y11
Source Sync
Input/Output
FERR#/PBE#
E27
Async GTL+
Output
Table 5-1. Pin Listing by Pin Name (cont’d)
Pin Name
Pin No.
Signal Buffer
Type
Direction
FORCEPR#
A15
Power/Other
Input
GTLREF0
W23
Power/Other
Input
GTLREF1
W9
Power/Other
Input
GTLREF2
F23
Power/Other
Input
GTLREF3
F9
Power/Other
Input
HIT#
E22
Common Clk
Input/Output
HITM#
A23
Common Clk
Input/Output
ID0#
A26
Common Clk
Input
ID1#
B26
Common Clk
Input
ID2#
D25
Common Clk
Input
ID3#
D27
Common Clk
Input
ID4#
C28
Common Clk
Input
ID5#
B29
Common Clk
Input
ID6#
B30
Common Clk
Input
ID7#
A30
Common Clk
Input
IDS#
A28
Common Clk
Input
IERR#
E5
Async GTL+
Output
IGNNE#
C26
Async GTL+
Input
INIT#
D6
Async GTL+
Input
LINT0/INTR
B24
Async GTL+
Input
LINT1/NMI
G23
Async GTL+
Input
LOCK#
A17
Common Clk
Input/Output
MCERR#
D7
Common Clk
Input/Output
ODTEN
B5
Power/Other
Input
OOD#
D29
Common Clk
Input
PROCHOT#
B25
Async GTL+
Output
PWRGOOD
AB7
Async GTL+
Input
REQ0#
B19
Source Sync
Input/Output
REQ1#
B21
Source Sync
Input/Output
REQ2#
C21
Source Sync
Input/Output
REQ3#
C20
Source Sync
Input/Output
REQ4#
B22
Source Sync
Input/Output
Reserved
A31
Reserved
C1
Reserved
E16
Reserved
W3
Reserved
Y27
Table 5-1. Pin Listing by Pin Name (cont’d)
Pin Name
Pin No.
Signal Buffer
Type
Direction