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| 型號(hào)： | 80546KF |
| 廠商： | Intel Corp. |
| 英文描述： | 64-bit Intel Xeon Processor MP with up to 8MB L3 Cache |
| 中文描述： | 64位Intel Xeon處理器MP的高達(dá)8MB三級(jí)高速緩存 |
| 文件頁數(shù)： | 87/138頁 |
| 文件大小： | 2666K |
| 代理商： | 80546KF |
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64-bit Intel
Xeon Processor MP with up to 8MB L3 Cache Datasheet
87
6
Signal Definitions
6.1
Signal Definitions
Table 6-1. Signal Definitions (Sheet 1 of 9)
Name
Type
Description
A[39:3]#
I/O
A[39:3]# (Address) define a 2
40
-byte physical memory address space. In sub-
phase 1 of the address phase, these pins transmit the address of a transaction.
In sub-phase 2, these pins transmit transaction type information. These signals
must connect the appropriate pins of all agents on the processor front side bus.
A[39:3]# are protected by parity signals AP[1:0]#. A[39:3]# are source
synchronous signals and are latched into the receiving buffers by
ADSTB[1:0]#.
On the active-to-inactive transition of RESET#, the processors sample a subset
of the A[39:3]# pins to determine their power-on configuration. See
Section 8.1
.
A20M#
I
If A20M# (Address-20 Mask) is asserted, the processor masks physical
address bit 20 (A20#) before looking up a line in any internal cache and before
driving a read/write transaction on the bus. Asserting A20M# emulates the
8086 processor's address wrap-around at the 1-Mbyte boundary. Assertion of
A20M# is only supported in real mode.
A20M# is an asynchronous signal. However, to ensure recognition of this signal
following an I/O write instruction, it must be valid 6 clks before the I/O write’s
response.
ADS#
I/O
ADS# (Address Strobe) is asserted to indicate the validity of the transaction
address on the A[39:3]# and transaction request type on REQ[4:0]# pins. All
bus agents observe the ADS# activation to begin parity checking, protocol
checking, address decode, internal snoop, or deferred reply ID match
operations associated with the new transaction. This signal must connect the
appropriate pins on all processor front side bus agents.
ADSTB[1:0]#
I/O
Address strobes are used to latch A[39:3]# and REQ[4:0]# on their rising and
falling edge.
AP[1:0]#
I/O
AP[1:0]# (Address Parity) are driven by the requestor one common clock after
ADS#, A[39:3]#, REQ[4:0]# are driven. A correct parity signal is electrically high
if an even number of covered signals are electrically low and electrically low if
an odd number of covered signals are electrically low. This allows parity to be
electrically high when all the covered signals are electrically high. AP[1:0]#
should connect the appropriate pins of all processor front side bus agents. The
following table defines the coverage for these signals.
BCLK[1:0]
I
The differential bus clock pair BCLK[1:0] determines the bus frequency. All
processor front side bus agents must receive these signals to drive their
outputs and latch their inputs.
All external timing parameters are specified with respect to the rising edge of
BCLK0 crossing the falling edge of BCLK1.
Request Signals
Subphase 1
Subphase 2
A[39:24]#
AP0#
AP1#
A[23:3]#
AP1#
AP0#
REQ[4:0]#
AP1#
AP0#
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