Clock Conditioning Circuits in IGLOO and ProASIC3 Devices
4- 4
v1.1
Global Buffers with No Programmable Delays
Access to the global / quadrant global networks can be configured directly from the global I/O
buffer, bypassing the CCC functional block (as indicated by the dotted lines in
Figure 4-2). Internal
signals driven by the FPGA core can use the global / quadrant global networks by connecting via
the routed clock input of the multiplexer tree.
There are many specific CLKBUF macros supporting the wide variety of single-ended I/O inputs
(CLKBUF) and differential I/O standards (CLKBUF_LVDS/LVPECL) in the low-power flash families.
They are used when connecting global I/Os directly to the global/quadrant networks.
When an internal signal needs to be connected to the global/quadrant network, the CLKINT macro
is used to connect the signal to the routed clock input of the network's MUX tree.
To utilize direct connection from global I/Os or from internal signals to the global/quadrant
networks, CLKBUF, CLKBUF_LVPECL/LVDS, and CLKINT macros are used.
The CLKBUF and CLKBUF_LVPECL/LVDS/BLVDS/M-LVDS macros are composite macros that
include an I/O macro driving a global buffer, which uses a hardwired connection.
The CLKBUF, CLKBUF_LVPECL/LVDS/BLVDS/M-LVDS, and CLKINT macros are pass-through
clock sources and do not use the PLL or provide any programmable delay functionality.
The CLKINT macro provides a global buffer function driven internally by the FPGA core.
The available CLKBUF macros are described in the
Global Buffer with Programmable Delay
Clocks requiring clock adjustments can utilize the programmable delay cores before connecting to
the global / quadrant global networks. A maximum of 18 CCC global buffers can be instantiated in
a device—three per CCC times up to six CCCs per device.
Each CCC functional block contains a programmable delay element for each of the global networks
(up to three).
Note: The CLKDLY macro uses programmable delay element type 2.
Figure 4-2 CCC Options: Global Buffers with No Programmable Delay
None
CLKBUF_LVDS/LVPECL Macro
PADN
PADP
YY
A
PAD
Y
CLKINT Macro
CLKBUF Macro
GLA
or
GLB
or
GLC
Clock Source
Clock Conditioning
Output