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ProASIC3/E SSO and Pin Placement Guidelines
21 – ProASIC3/E SSO and Pin Placement Guidelines
Introduction
Ground bounce and VCC bounce have always been present in digital integrated circuits (ICs). With
the advance of technology and shrinking CMOS features, the speed of designs, I/O slew rates, and
the size of I/O busses have increased significantly in the past few years. As a result, simultaneously
switching outputs (SSOs) and their effects on signal integrity have become an important factor in
any digital IC design. When SSOs are not properly designed into a board layout or digital IC, data
corruption and system failure may result.
To prevent SSO-induced issues in modern digital systems, designers must compromise an elegant
board layout for reliability. An elegant board layout may include practices such as placing all inputs
on one side of a chip, outputs on the opposite side, and all bus pins next to each other to make
board layout simple. In today's digital systems, utilizing modern FPGAs such as Actel ProASIC3/E
may result in data corruption due to ground bounce, VCC bounce, or crosstalk. To design a reliable
system for ProASIC3/E FPGAs, follow three simple rules:
1. Identify the SSOs in a design as early in the design cycle as possible, and spread them out
across the entire die periphery. Avoid clusters of more than four adjacent SSO pins.
2. Identify sensitive (and usually asynchronous) system signals, and shield them from the
effects of SSO (specific shielding techniques are discussed later in this document).
3. Use the lowest possible I/O slew rate and drive strength the design timing will support.
Furthermore, relatively large lead inductance in PQ, TQ, and VQ packages makes these packages
more vulnerable to SSOs and hence undesirable for high-speed designs or designs with a
considerable number of SSOs. FG or BG packages are preferred in such designs because they show
much better SSO performance. By following the above three rules, you will create reliable systems
free from the effects of SSOs. The following sections cover specific SSO recommendations and
mitigation techniques for designs that do not comply with these recommendations.
SSO Effects
The total number of SSOs for each bus is determined by identifying the outputs that are
synchronous to a single clock domain, have their clock-to-out times within ±200 ps of each other,
and are placed next to each other on die pads that are on both sides of a sensitive I/O, as shown in
I/O or quiet I/O. SSOs may affect the victim I/O if the total number of SSOs on both sides of the
victim I/O exceeds the ProASIC3/E SSO recommendation. It is important to note that the SSOs
should be referenced to the die pads and not package pins, since neighboring package pins are not
necessarily next to each other on the die (e.g., for BG and FG packages). This can be determined by
using MultiView Navigator (MVN) in the Designer software, or die/package bonding diagrams
provided by Actel. However, when routing traces on the board, it is important to note that SSOs on
neighboring traces on the board may affect the quiet I/O surrounded by the SSO traces due to
crosstalk or coupling.