參數(shù)資料
型號(hào)： AD6635BB
廠商： ANALOG DEVICES INC
元件分類： 無(wú)繩電話/電話
英文描述： 4-Channel, 80 MSPS WCDMA Receive Signal Processor (RSP)
中文描述： TELECOM, CELLULAR, BASEBAND CIRCUIT, PBGA324
封裝： 19 X 19 MM, PLASTIC, BGA-324
文件頁(yè)數(shù)： 2/60頁(yè)
文件大小： 799K
代理商： AD6635BB
REV. 0
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AD6635
GENERAL DESCRIPTION
The AD6635 is a multimode, 8-channel, digital Receive Signal
Processor (RSP) capable of processing up to four WCDMA
channels. Each channel consists of four cascaded signal-process-
ing elements: a frequency translator, two CIC decimating filters,
and a programmable coefficient-decimating filter. Each input
port has input level threshold detection circuitry for accommo-
dating large dynamic ranges or situations where gain ranging
converters are used. Quad 16-bit parallel output ports accom-
modate high data rate WBCDMA applications. On-chip
interpolating half-band filters can also be used to further
increase the output rate. In addition, each output port has a
digital AGC for accommodating large dynamic ranges using
smaller bit widths. The AGCs can maintain either signal level or
clipping level, depending on their mode. Link port outputs are
provided to enable glueless interfaces to Analog Devices’
TigerSHARC DSP core.
The AD6635 is part of Analog Devices’ SoftCell Multicarrier
transceiver chipset designed for compatibility with Analog Devices’
family of high sample rate IF sampling ADCs (AD9238/AD6645
12-bit and 14-bit). The SoftCell receiver comprises a digital
receiver capable of digitizing an entire spectrum of carriers and
digitally selecting the carrier of interest for tuning and channel
selection. This architecture eliminates redundant radios in wireless
base station applications.
High dynamic range decimation filters offer a wide range of
decimation rates. The RAM-based architecture allows easy
reconfiguration for multimode applications.
The decimating filters remove unwanted signals and noise from
the channel of interest. When the channel of interest occupies
less bandwidth than the input signal, this rejection of out-of-band
noise is called “processing gain.” By using large decimation
factors, processing gain can improve the SNR of the ADC by
30 dB or more. In addition, the programmable RAM coefficient
filter allows antialiasing, matched filtering, and static equaliza-
tion functions to be combined in a single, cost-effective filter.
Half-band interpolating filters at the output are used in various
applications, especially in WCDMA or cdma2000 applications,
to increase the output rate from 2
￥
to 4
￥
the chip rate. The
AD6635 is equipped with four independent automatic gain
control (AGC) loops for direct interface to a RAKE receiver.
The AD6635 is compatible with standard ADC converters, such
as the AD664x, AD943x, AD923x, and the AD922x families of
data converters. The AD6635 is also compatible with the
AD6600 Diversity ADC, and hence can be designed into exist-
ing systems that use AD6600 ADCs.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD6635BB/PCB 制造商:Analog Devices 功能描述:Evaluation Kit For 4-Channel, 80MSPS WCDMA Receive Signal Processor
AD6635BBZ 制造商:Analog Devices 功能描述:Receive Signal Processor 324-Pin BGA
AD6636 制造商:AD 制造商全稱:Analog Devices 功能描述:150 MSPS Wideband Digital Down-Converter (DDC)
AD6636BBC 制造商:Analog Devices 功能描述:Digital Down Converter 256-Pin CSP-BGA
AD6636BBCZ 功能描述:IC DIGITAL DWNCONV 6CH 256CSPBGA RoHS:是 類別:RF/IF 和 RFID >> RF 混頻器 系列:AD6636 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:100 系列:- RF 型:W-CDMA 頻率:2.11GHz ~ 2.17GHz 混頻器數(shù)目:1 增益:17dB 噪音數(shù)據(jù):2.2dB 次要屬性:- 電流 - 電源:11.7mA 電源電壓:2.7 V ~ 3.3 V 包裝:托盤 封裝/外殼:12-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:12-QFN-EP（3x3）
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