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參數(shù)資料
| 型號(hào)： | AD6635BB |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 無繩電話/電話 |
| 英文描述： | 4-Channel, 80 MSPS WCDMA Receive Signal Processor (RSP) |
| 中文描述： | TELECOM, CELLULAR, BASEBAND CIRCUIT, PBGA324 |
| 封裝： | 19 X 19 MM, PLASTIC, BGA-324 |
| 文件頁數(shù)： | 47/60頁 |
| 文件大?。?/td> | 799K |
| 代理商： | AD6635BB |
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REV. 0
AD6635
–47–
is prior to the ADC, there is a latency associated with the ADC
and with the settling of the gain change. This register allows the
internal delay of the LIA-A and LIA-B signal to be programmed.
0x04 Lower Threshold B
This word is 10 bits wide and maps to the 10 MSBs of the
mantissa. If the upper 10 bits of Input Port B are less than or
equal to this value, the lower threshold has been met. In nor-
mal chip operation, this starts the dwell time counter. If the
input signal increases above this value, the counter is reloaded
and waits for the input to drop back to this level.
0x05 Upper Threshold B
This word is 10 bits wide and maps to the 10
MSBs
of the
mantissa. If the upper 10 bits of Input Port B are greater than
or equal to this value, the upper threshold has been met. In
normal chip operation, this will cause the appropriate LI pin
(LIB-A or LIB-B) to become active.
0x06 Dwell Time B
This sets the time that the input signal must be at or below the
lower threshold before the LI pin is deactivated. For the input
level detector to work, the dwell time must be set to at least 1. If
set to 0, the LI functions are disabled.
This is a 20-bit register. When the lower threshold is met fol-
lowing an excursion into the upper threshold, the dwell time
counter is loaded and begins to count high speed clock cycles as
long as the input is at or below the lower threshold. If the signal
increases above the lower threshold, the counter is reloaded and
waits for the signal to fall below the lower threshold again.
0x07 Gain Range B Control Register
Bit 4 determines the polarity of LIB-A and LIB-B. If this bit
is clear, the LI signal is high when the upper threshold has
been exceeded. However, if this bit is set, the LI pin is low
when active. This allows maximum flexibility when using
this function.
Bit 3 determines if the input consists of a single channel or
TDM channels, such as when using the AD6600. If this bit is
cleared, a single ADC is assumed. In this mode, LIB-A func-
tions as the active output indicator. LIB-B provides the
compliment of LIB-A. However, if this bit is set, the input is
determined to be dual-channel and determined by the state of
the IENB pin. If the IENB pin is low, the input detection is
directed to LIB-A. If the IENB pin is high, the input is directed
to LIB-B. In either case, Bit 4 determines the actual polarity of
these signals.
Bits 2–0 determine the internal latency of the gain detect func-
tion. When the LIB-A and LIB-B pins are made active, they are
typically used to change an attenuator or gain stage. Since this is
prior to the ADC, there is a latency associated with the ADC and
with the settling of the gain change. This register allows the inter-
nal delay of the LIB-A and LIB-B signal to be programmed.
Table XV. Memory Map for Output Port Control Registers
Channel Address (hex)
Register
Bit Width
Comments
08
Port A Control Register
4
3: Port A Enable
2–1: HB A Signal Interleaving
11
All 4 Channels
10
Channels 0, 1, 2
01
Channels 0, 1
00
Channel 0
0: Bypass
2: Port B Enable
1: HB A Signal Interleaving
1
Channels 2, 3
0
Channel 2
0: Bypass
7–5: Output Word Length
111
4 bits
110
5 bits
101
6 bits
100
7 bits
011
8 bits
010
10 bits
001
12 bits
000
16 bits
09
Port B Control Register
3
0A
AGC A Control Register
8
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| AD6635BB/PCB | 制造商:Analog Devices 功能描述:Evaluation Kit For 4-Channel, 80MSPS WCDMA Receive Signal Processor |
| AD6635BBZ | 制造商:Analog Devices 功能描述:Receive Signal Processor 324-Pin BGA |
| AD6636 | 制造商:AD 制造商全稱:Analog Devices 功能描述:150 MSPS Wideband Digital Down-Converter (DDC) |
| AD6636BBC | 制造商:Analog Devices 功能描述:Digital Down Converter 256-Pin CSP-BGA |
| AD6636BBCZ | 功能描述:IC DIGITAL DWNCONV 6CH 256CSPBGA RoHS:是 類別:RF/IF 和 RFID >> RF 混頻器 系列:AD6636 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:100 系列:- RF 型:W-CDMA 頻率:2.11GHz ~ 2.17GHz 混頻器數(shù)目:1 增益:17dB 噪音數(shù)據(jù):2.2dB 次要屬性:- 電流 - 電源:11.7mA 電源電壓:2.7 V ~ 3.3 V 包裝:托盤 封裝/外殼:12-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:12-QFN-EP（3x3） |
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