參數(shù)資料
型號： AD6635BB
廠商： ANALOG DEVICES INC
元件分類： 無繩電話/電話
英文描述： 4-Channel, 80 MSPS WCDMA Receive Signal Processor (RSP)
中文描述： TELECOM, CELLULAR, BASEBAND CIRCUIT, PBGA324
封裝： 19 X 19 MM, PLASTIC, BGA-324
文件頁數(shù)： 44/60頁
文件大?。?/td> 799K
代理商： AD6635BB
REV. 0
–44–
AD6635
Table XI. Channel Memory Map (continued)
Channel Address
Register
Bit Width
Comments
A5
A6
A7
A8
BIST Signature for I path
BIST Signature for Q path
# of BIST outputs to accumulate
RAM BIST Control Register
16
16
20
3
BIST-I
BIST-Q
19–0: # of outputs (Counter Value Read)
2: D-RAM Fail/Pass
1: C-RAM Fail/Pass
0: RAM BIST Enable
9: Map RCF Data to BIST Registers
5: Output Format
1: 16-bit I and 16-bit Q
0: 12-bit I and 12-bit Q
A9
Output Control Register
0x90: rCIC2 Decimation – 1 (M
rCIC2
– 1)
This register is used to set the decimation in the rCIC2 filter.
The value written to this register is the decimation minus 1. The
rCIC2 decimation can range from 1 to 4096, depending upon
the interpolation of the channel. The decimation must always be
greater than the interpolation. M
rCIC2
must be chosen larger
than L
rCIC2
and both must be chosen such that a suitable rCIC2
scalar can be chosen. For more details, see the Second-Order
rCIC2 Filter section.
0x91: rCIC2 Interpolation – 1 (L
rCIC2
-1)
This register is used to set the interpolation in the rCIC2 filter.
The value written to this register is the interpolation minus 1.
The rCIC2 interpolation can range from 1 to 512, depending
upon the decimation of the rCIC2. There is no timing error
associated with this interpolation. For more details, see the
Second-Order rCIC2 Filter section.
0x92: rCIC2 Scale
The rCIC2 scale register is used to provide attenuation to com-
pensate for the gain of the rCIC2, and to adjust the linearization
of the data from the floating-point input. The use of this scale
register is influenced both by the rCIC2 growth and floating-
point input port considerations. For more details, see the
Second-Order rCIC2 Filter section.
The rCIC2 scalar has been combined with the exponent offset
and will need to be handled appropriately in both the input port
and rCIC2 sections.
Bit 11 determines the polarity of the exponent. Normally, this
bit will be cleared unless an ADC such as the AD6600 is used,
in which case this bit will be set.
Bit 10 determines the weight of the exponent word associated
with the input port. When this bit is low, each exponent step is
considered to be worth 6.02 dB. When this bit is high, each
exponent step is considered to be worth 12.02 dB.
Bits 9–5 are the actual scale value used when the level indicator
(LI) pin associated with this channel is active.
Bits 4–0 are the actual scale value used when the level indicator
(LI) pin associated with this channel is active.
0x93:
Reserved. (Must be written low.)
0x94: CIC5 Decimation – 1 (M
CIC5
– 1)
This register is used to set the decimation in the CIC5 filter.
The value written to this register is the decimation minus 1.
Although this is an 8-bit register, the decimation is usually lim-
ited between 1 and 32. Decimations higher than 32 require
more scaling than the CIC5 is capable of.
0x95: CIC5 Scale
The CIC5 scale factor is used to compensate for the growth of
the CIC5 filter. Consult the Fifth-Order CIC5 filter section
for details.
0x96:
Reserved. (Must be written low.)
0xA0: RCF Decimation – 1 (M
RCF
– 1)
This register is used to set the decimation of the RCF stage. The
value written is the decimation minus 1. Although this is an
8-bit register that allows decimation up to 256, for most fil-
tering scenarios the decimation should be limited between 1 and
32. Higher decimations are allowed, but the alias protection of
the RCF may not be acceptable for some applications.
0xA1: RCF Decimation Phase (P
RCF
)
This register allows any one of the M
RCF
phases of the filter to
be used, and can be adjusted dynamically. Each time a filter is
started, this phase is updated. When a channel is synchronized,
it will retain the phase setting chosen here. This can be used as
part of a timing recovery loop with an external processor, or can
allow multiple RCFs to work together while using a single RCF
pair. Consult the RAM Coefficient Filter (RCF) section for
further details.
0xA2: RCF Number of Taps Minus 1 (N
RCF
– 1)
The number of taps for the RCF filter minus 1 is written here.
0xA3: RCF Coefficient Offset (CO
RCF
)
This register is used to specify which section of the 256-word
coefficient memory is used for a filter. It can be used to select
between multiple filters that are loaded into memory and refer-
enced by this pointer. This register is shadowed and the filter
pointer is updated every time a new filter is started. This allows
the coefficient offset to be written even while a filter is being
computed without disturbing operation. The next sample that
comes out of the RCF will be with the new filter.
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相關代理商/技術參數(shù)
參數(shù)描述
AD6635BB/PCB 制造商:Analog Devices 功能描述:Evaluation Kit For 4-Channel, 80MSPS WCDMA Receive Signal Processor
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AD6636BBC 制造商:Analog Devices 功能描述:Digital Down Converter 256-Pin CSP-BGA
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