參數(shù)資料
型號(hào)： AD6635BB
廠商： ANALOG DEVICES INC
元件分類： 無繩電話/電話
英文描述： 4-Channel, 80 MSPS WCDMA Receive Signal Processor (RSP)
中文描述： TELECOM, CELLULAR, BASEBAND CIRCUIT, PBGA324
封裝： 19 X 19 MM, PLASTIC, BGA-324
文件頁(yè)數(shù)： 42/60頁(yè)
文件大?。?/td> 799K
代理商： AD6635BB
REV. 0
–42–
AD6635
Each individual channel of the AD6635 has a separate channel
memory map. These memory maps are addressed by using the
appropriate chip select pin (
CS0
,
CS1
) and writing the appro-
priate 2-bit address in the two LSBs of external address 7. If
CS0
is used for programming, 00 in these two bits accesses the
memory map of Channel 0, 01 accesses that of Channel 1, 10
accesses that of Channel 2, and 11 accesses that of Channel 3.
If
CS1
is used, 00 corresponds to Channel 4, 01 to Channel 5,
10 to Channel 6, and 11 to Channel 7. It should be noted that
when doing this, Bit 5 of external address 3 (access input/out-
put control registers) is not enabled.
0x00–0x7F: Coefficient Memory (CMEM)
This is the Coefficient Memory (CMEM) used by the RCF. It
is memory mapped as 128 words 20 bits. A second 128
words of RAM may be accessed via this same location by writ-
ing Bit 8 of the RCF control register high at channel address
0xA4. The filter calculated will always use the same coefficients
for I and Q. By using memory from both of these 128 blocks, a
filter up to 160 taps can be calculated. Multiple filters can be
loaded and selected with a single internal access to the Coeffi-
cient Offset register at channel address 0xA3.
0x80: Channel Sleep Register
This register contains the SLEEP bit for the channel. When this
bit is high, the channel is placed in a low power state. When this
bit is low, the channel processes data. This bit can also be set
by accessing the SLEEP register at external address 3. When
the External SLEEP register is accessed, all four channels are
accessed simultaneously and the SLEEP bits of the channels are
set appropriately.
0x81: Soft_SYNC Register
This register is used to initiate SYNC events through the
microport. If the Hop bit is written high, then the Hop Holdoff
counter at address 0x84 is loaded and begins to count down.
When this value reaches 1, the NCO Frequency register used
by the NCO accumulator is loaded with the data from channel
addresses 0x85 and 0x86. When the Start bit is set high, the
Start Holdoff Counter is loaded with the value at address 0x83
and begins to count down. When this value reaches 1, the Sleep
bit in address 0x80 is dropped low and the channel is started.
0x82: Pin_SYNC Register
This register is used to control the functionality of the SYNC
pins. Any of the four SYNC pins can be chosen and monitored
by the channel. The channel can be configured to initiate either
a Start or Hop SYNC event by setting the Hop or Start bit
high. These bits function as enables so that when a SYNC pulse
occurs, either the Start or Hop Holdoff counters are activated
in the same manner as with a Soft_SYNC.
0x83: Start Holdoff Counter
The Start Holdoff counter is loaded with the value written to
this address when a Start_Sync is initiated. It can be initiated
by either a Soft_SYNC or Pin_SYNC. The counter begins
decrementing and when it reaches a value of 1, the channel is
brought out of SLEEP and begins processing data. If the chan-
nel is already running, then the phase of the filters are adjusted
such that multiple AD6635s can be synchronized. A periodic
pulse on the SYNC pin can be used in this way to adjust the
timing of the filters with the resolution of the ADC sample
clock. If this register is written to a 1, the Start will occur imme-
diately when the SYNC comes into the channel. If it is written
to a 0, no SYNC will occur.
0x84: NCO Frequency Holdoff Counter
The NCO Frequency Holdoff counter is loaded with the value
written to this address when either a Soft_SYNC or Pin_SYNC
comes into the channel. The counter begins counting down so
that when it reaches 1, the NCO frequency word is updated
with the values of addresses 0x85 and 0x86. This is known as a
Hop or Hop_SYNC. If this register is written to a 1, the NCO
frequency will be updated immediately when the SYNC comes
into the channel. If it is written to a 0, no hop will occur. NCO
hops can be either phase continuous or nonphase continuous,
depending upon the state of Bit 3 of the NCO Control register
at channel address 0x88. When this bit is low, the Phase Accu-
mulator of the NCO is not cleared but starts to add the new
NCO frequency word to the accumulator as soon as the SYNC
occurs. If this bit is high, the Phase Accumulator of the NCO is
cleared to 0 and the new word is then accumulated.
0x85: NCO Frequency Register 0
This register represents the 16 LSBs of the NCO frequency
word. These bits are shadowed and are not updated to the regis-
ter used for the processing until the channel is either brought
out of SLEEP, or a Soft_SYNC or Pin_SYNC has been issued.
In the latter two cases, the register is updated when the Fre-
quency Holdoff counter hits a value of 1. If the Frequency
Holdoff counter is set to 1, the register will be updated as soon
as the shadow is written.
0x86: NCO Frequency Register 1
This register represents the 16 MSBs of the NCO Frequency
word. These bits are shadowed and are not updated to the regis-
ter used for the processing until the channel is either brought
out of SLEEP, or a Soft_SYNC or Pin_SYNC has been issued.
In the latter two cases, the register is updated only when the
Frequency Holdoff counter hits a value of 1. If the Frequency
Holdoff counter is set to 1, the register will be updated as soon
as the shadow is written.
0x87: NCO Phase Offset Register
This register represents a 16-bit phase offset to the NCO. It is
interpreted as values ranging from 0 radians to 2 (216 – 1)/
(216) radians.
0x88: NCO Control Register
This 9-bit register controls features of the NCO and the chan-
nel. The bits are defined below. The numerically controlled
oscillator (NCO) section should be consulted for more detail.
Bits 8–7 of this register choose which of the four SYNC pins are
used by the channel. The SYNC pin selected can be used to
initiate a start, hop, or timing adjustment to the channel. The
Synchronization section provides more details.
Bit 6 of this register defines the input used by the channel. For
Channels 0 to 3, the input port can be A or B, while for Chan-
nels 4 to 7, the Input port can be C or D. For Channels 0 to 3,
if this bit is low, input Port A is selected, and if this bit is high,
Input Port B is selected. For Channels 4 to 7, if this bit is low,
Input Port C is selected, and if this bit is high, Input Port D is
selected. Each channel can select its input port individually.
Each input port consists of a 14-bit input mantissa (INx[13:0]),
a 3-bit exponent(EXPx[2:0]), and an input enable pin IENx.
The x represents either A, B, C, or D.
Bits 5–4 determine how the sample clock for the channel is
derived from the high speed CLK signal. There are four possible
choices. Each is defined below; for further detail the numerically
controlled oscillator (NCO) section.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD6635BB/PCB 制造商:Analog Devices 功能描述:Evaluation Kit For 4-Channel, 80MSPS WCDMA Receive Signal Processor
AD6635BBZ 制造商:Analog Devices 功能描述:Receive Signal Processor 324-Pin BGA
AD6636 制造商:AD 制造商全稱:Analog Devices 功能描述:150 MSPS Wideband Digital Down-Converter (DDC)
AD6636BBC 制造商:Analog Devices 功能描述:Digital Down Converter 256-Pin CSP-BGA
AD6636BBCZ 功能描述:IC DIGITAL DWNCONV 6CH 256CSPBGA RoHS:是 類別:RF/IF 和 RFID >> RF 混頻器 系列:AD6636 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:100 系列:- RF 型:W-CDMA 頻率:2.11GHz ~ 2.17GHz 混頻器數(shù)目:1 增益:17dB 噪音數(shù)據(jù):2.2dB 次要屬性:- 電流 - 電源:11.7mA 電源電壓:2.7 V ~ 3.3 V 包裝:托盤 封裝/外殼:12-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:12-QFN-EP（3x3）
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