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參數(shù)資料
| 型號(hào)： | AD6635BB |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 無繩電話/電話 |
| 英文描述： | 4-Channel, 80 MSPS WCDMA Receive Signal Processor (RSP) |
| 中文描述： | TELECOM, CELLULAR, BASEBAND CIRCUIT, PBGA324 |
| 封裝： | 19 X 19 MM, PLASTIC, BGA-324 |
| 文件頁數(shù)： | 24/60頁 |
| 文件大?。?/td> | 799K |
| 代理商： | AD6635BB |
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REV. 0
–24–
AD6635
would be to provide a flag that could be used to quickly insert
an attenuator that would prevent ADC overdrive. If 18 dB (or
any other arbitrary value) of attenuation is switched in, then the
signal dynamic range of the system will have been increased by
18 dB. The process begins when the input signal reaches the
upper programmed threshold. In a typical application, this may
be set 1 dB (user definable) below full scale. When this input
condition is met, the appropriate LI signal (LIA-A, LIB-A, LIC-A,
or LID-A) associated with its corresponding input port (A through
D) is made active. This can be used to switch the gain or attenua-
tion of the external circuit. The LI line stays active until the input
condition falls below the lower programmed threshold. To provide
hysteresis, a dwell time register (see Memory Map for Input Con-
trol Registers) is available to hold off switching of the control line
for a predetermined number of clocks. Once the input condition is
below the lower threshold, the programmable counter begins
counting high speed clocks. As long as the input signal stays
below the lower threshold for the number of high speed clock
cycles programmed, the attenuator will be removed on the
terminal count. However, if the input condition goes above
the lower threshold with the counter running, the counter is
reset and input must fall below the lower threshold again to
initiate the process. This will prevent unnecessary switching
between states.
This is illustrated in Figure 26. When the input signal goes
above the upper threshold, the appropriate LI signal becomes
active. Once the signal falls below the lower threshold, the
counter begins counting. If the input condition goes above the
lower threshold, the counter is reset and starts again as shown.
Once the counter has terminated to 0, the LI line goes inactive.
“HIGH”
M
DWELL TIME
“LOW”
UPPER
THRESHOLD
LOWER
THRESHOLD
COUNTER
RESTARTS
TIME
Figure 26. Threshold Settings for LI
The LI line can be used for a variety of functions. It can be used
to set the controls of an attenuator, DVGA, or it can be inte-
grated and used with an analog VGA. To simplify the use of this
feature, the AD6635 includes two separate gain settings, one
when this LI line is inactive (rCIC2_QUIET[4:0] stored in Bits 9:5
of 0x92 register) and the other when active (rCIC2_LOUD[4:0]
stored in Bits 4:0 of 0x92 register). This allows the digital gain to
be adjusted to the external changes. In conjunction with the
gain setting, a variable holdoff is included to compensate for the
pipeline delay of the ADC and the switching time of the gain
control element. Together, these two features provide seamless
gain switching.
Another use of this pin is to facilitate a gain-range holdoff within a
gain-ranging ADC. For converters that use gain-ranging to
increase total signal dynamic range, it may be desirable to prohibit
internal gain ranging from occurring in some instances. For such
converters, the LI (A or B) line can be used to hold this off. For
this application, the upper threshold would be set based on similar
criteria. However, the lower threshold would be set to a level
consistent with the gain ranges of the specific converter. Then
the holdoff delay can be set appropriately for any of a number of
factors, such as fading profile, signal peak-to-average ratio, or
any other time based characteristics that might cause unnecessary
gain changes.
The AD6635 has a total of eight gain control circuits to support
all channels, and hence can be used even when all input ports
have interleaved data. When data is interleaved on a certain
input port, the appropriate bit should be set in the Gain Range
Control Register. This way both interleaved channel data can be
monitored, and LIA-B, LIB-B, LIC-B, or LID-B pins associ-
ated with their corresponding Input Ports A through D act as
output indicators for the interleaved channel. LIx-A pins act as
indicators for input data corresponding to IENx Low, and LIx-B
act as indicators for input data corresponding to IENx High in
this mode. When interleaved channels are not used, LIx-B pins
are complimentary to LIx-A pins acting as indicators with oppo-
site polarity. It should be noted that the gain control circuits are
wideband and are implemented prior to any filtering elements to
minimize loop delay.
The chip also provides appropriate scaling of the internal data
based on the attenuation associated with the LI signal. In this
manner, data to the DSP maintains a correct scale value through-
out the process, making it entirely independent. Since there
often are finite delays associated with external gain switching
components, the AD6635 includes a variable pipeline delay that
can be used to compensate for external pipeline delays or gross
settling times associated with gain/attenuator devices. This delay
may be set for up to seven high speed clocks. These features
ensure smooth switching between gain settings.
Input Data Scaling
The AD6635 has four data input ports. Each accepts a 14-bit
mantissa (twos complement integer) IN[13:0], a 3-bit exponent
(unsigned integer) EXP[2:0], and the Input Enable(IEN). Input
Ports A and B are clocked by CLK0 and Input Ports C and D
are clocked by CLK1. These pins allow direct interfacing to both
standard fixed-point ADCs such as the AD9238 and AD6645, as
well as to gain-ranging ADCs such as the AD6600. For normal
operation with ADCs having fewer than 14 bits, the active bits
should be MSB justified and the unused LSBs should be tied low.
The 3-bit exponent, EXP[2:0] is interpreted as an unsigned
integer. The exponent will subsequently be modified by either
of rCIC2_LOUD[4:0] or rCIC2_QUIET[4:0], depending on
whether the LI line is active or not. These 5-bit scale values are
stored in the rCIC2 scale register (0x92) and the scaling is applied
before the data enters the rCIC2 resampling filter. These 5-bit
registers contain scale values to compensate for the rCIC2 gain,
external attenuator (if used), and the Exponent Offset (Expoff). If
no external attenuator is used, both the rCIC2_QUIET and
rCIC2_LOUD registers contain the same value. A detailed
explanation and equation for setting the attenuating scale
register is given in the Scaling with Floating-Point ADCs section.
Scaling with Fixed-Point ADCs
For fixed-point ADCs the AD6635 exponent inputs, EXP[2:0],
are typically not used and should be tied low. The ADC outputs
are tied directly to the AD6635 inputs, MSB-justified. The
ExpOff bits in 0x92 should be programmed to 0. Likewise, the
Exponent Invert bit should be 0. Thus for fixed-point ADCs,
the exponents are typically static and no input scaling is used in
the AD6635.
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| AD6635BB/PCB | 制造商:Analog Devices 功能描述:Evaluation Kit For 4-Channel, 80MSPS WCDMA Receive Signal Processor |
| AD6635BBZ | 制造商:Analog Devices 功能描述:Receive Signal Processor 324-Pin BGA |
| AD6636 | 制造商:AD 制造商全稱:Analog Devices 功能描述:150 MSPS Wideband Digital Down-Converter (DDC) |
| AD6636BBC | 制造商:Analog Devices 功能描述:Digital Down Converter 256-Pin CSP-BGA |
| AD6636BBCZ | 功能描述:IC DIGITAL DWNCONV 6CH 256CSPBGA RoHS:是 類別:RF/IF 和 RFID >> RF 混頻器 系列:AD6636 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:100 系列:- RF 型:W-CDMA 頻率:2.11GHz ~ 2.17GHz 混頻器數(shù)目:1 增益:17dB 噪音數(shù)據(jù):2.2dB 次要屬性:- 電流 - 電源:11.7mA 電源電壓:2.7 V ~ 3.3 V 包裝:托盤 封裝/外殼:12-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:12-QFN-EP（3x3） |
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