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| 型號： | AD6635BB |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 無繩電話/電話 |
| 英文描述： | 4-Channel, 80 MSPS WCDMA Receive Signal Processor (RSP) |
| 中文描述： | TELECOM, CELLULAR, BASEBAND CIRCUIT, PBGA324 |
| 封裝： | 19 X 19 MM, PLASTIC, BGA-324 |
| 文件頁數(shù)： | 29/60頁 |
| 文件大小： | 799K |
| 代理商： | AD6635BB |
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REV. 0
AD6635
–29–
of L/M that yields 0.25 will work (1/4, 2/8, or 4/16). However,
for the best dynamic range, the simplest ratio should be used.
For example, 1/4 gives better performance than 4/16.
Decimation and Interpolation Registers
rCIC2 decimation values are stored in register 0x90. This 12-bit
register contains the decimation portion less 1. The interpola-
tion portion is stored in register 0x91. This 9-bit value holds the
interpolation less 1.
rCIC2 Scale
Register 0x92 contains the scaling information for this section of
the circuit. The primary function is to store the scale value
computed in the sections above.
Bits 4–0 (rCIC2_LOUD[4:0]) of this register are used to contain
the scaling factor for the rCIC2 during conditions of strong
signals. These five bits represent the rCIC2 scalar calculated
above, plus any external signal scaling with an attenuator.
Bits 9–5 (rCIC2_QUIET[4:0]) of this register are used to con-
tain the scaling factor for the rCIC2 during conditions of weak
signals. In this register, no external attenuator would be consid-
ered and is not included. Only the value computed above for
rCIC2 compensation is stored in these bits.
Bit 10 of this register is used to indicate the value of the external
exponent. If this bit is set low, then external exponent represents
6 dB per step as in the AD6600. If this bit is set high, each
exponent represents a 12 dB step.
Bit 11 of this register is used to invert the external exponent
before internal calculation. This bit should be set high for gain-
ranging ADCs that use an increasing exponent to represent an
increasing signal level. This bit should be set low for gain-ranging
ADCs that use a decreasing exponent for representing an
increasing signal level.
In applications that do not require the features of the rCIC2, it
may be bypassed by setting the L/M ratio to 1/1. This effectively
bypasses all circuitry of the rCIC2 except the scaling which is
still in effect.
FIFTH-ORDER CIC FILTER
The third signal processing stage, CIC5, implements a sharper,
fixed-coefficient, decimating filter sharper than rCIC2. The
input rate to this filter is f
SAMP2
. The maximum input rate to this
filter is equal to the input rate into the AD6635, so bypassing
the rCIC2 filter is allowed.
The decimation ratio, MCIC5, may be programmed from 2 to
32 (all integer values). The frequency response of the filter is
given by the following equations. The gain and passband droop
of CIC5 should be calculated by these equations. Both parameters
may be compensated for in the RCF stage.
H( )
z
–
ê
z
H f
M
f
f
f
f
SCIC
2
MCIC
SCIC
2
CIC
SAMP
SAMP
–
sin
sin
–
–
=
￥ê
ê
á
á
á
á
ˉ
=
￥
￥
ˉ
ê
ˉ
ˉ
+
+
1
1
1
1
55
5
1
5
55
5
2
2
p
p
The scale factor SCIC5 is a programmable, unsigned integer
between 0 and 20. It serves to control the attenuation of the
data into the CIC5 stage in 6 dB increments. For the best dynamic
range, SCIC5 should be set to the smallest value possible (low-
est attenuation) without creating an overflow condition. This
can be safely accomplished using the equation below, where
OLrCIC2 is the largest fraction of full scale possible at the input
to this filter stage. This value is output from the rCIC2 stage,
then pipelined into the CIC5.
(
=
(
+
S
ceil
M
)
￥
OL
OL
M
OL
CIC
CIC
CIC
CIC
CIC
SCIC
2
CIC
5
2
5
2
5
5
5
55
5
5
=
￥
)
(
)
log
–
The output rate of this stage is given by the equation below.
f
f
M
SAMP
SAMP
CIC
5
5
5
=
CIC5 Rejection
Table IV illustrates the amount of bandwidth in percentage of the
clock rate (input rate) that can be protected with various decima-
tion rates and alias rejection specifications. The maximum input
rate into the CIC5 is 80 MHz when the rCIC2 decimates by 1. As
in the previous table, these are the 1/2 bandwidth characteristics
of the CIC5. Notice that the CIC5 stage can protect a much wider
band to any given rejection level compared to the rCIC2 stage.
This table helps to calculate an upper bound on decimation,
M
CIC5
, for given desired filter characteristics.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD6635BB/PCB | 制造商:Analog Devices 功能描述:Evaluation Kit For 4-Channel, 80MSPS WCDMA Receive Signal Processor |
| AD6635BBZ | 制造商:Analog Devices 功能描述:Receive Signal Processor 324-Pin BGA |
| AD6636 | 制造商:AD 制造商全稱:Analog Devices 功能描述:150 MSPS Wideband Digital Down-Converter (DDC) |
| AD6636BBC | 制造商:Analog Devices 功能描述:Digital Down Converter 256-Pin CSP-BGA |
| AD6636BBCZ | 功能描述:IC DIGITAL DWNCONV 6CH 256CSPBGA RoHS:是 類別:RF/IF 和 RFID >> RF 混頻器 系列:AD6636 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:100 系列:- RF 型:W-CDMA 頻率:2.11GHz ~ 2.17GHz 混頻器數(shù)目:1 增益:17dB 噪音數(shù)據(jù):2.2dB 次要屬性:- 電流 - 電源:11.7mA 電源電壓:2.7 V ~ 3.3 V 包裝:托盤 封裝/外殼:12-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:12-QFN-EP（3x3） |
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