參數(shù)資料
型號： AD6635BB
廠商： ANALOG DEVICES INC
元件分類： 無繩電話/電話
英文描述： 4-Channel, 80 MSPS WCDMA Receive Signal Processor (RSP)
中文描述： TELECOM, CELLULAR, BASEBAND CIRCUIT, PBGA324
封裝： 19 X 19 MM, PLASTIC, BGA-324
文件頁數(shù)： 52/60頁
文件大?。?/td> 799K
代理商： AD6635BB
REV. 0
–52–
AD6635
0x17 AGC B Pole Location
This 8-bit register is used to define the open loop filter pole
location ‘P.’ Its value can be set from 0 to 0.996 in steps of
0.0039. This value of ‘P’ is updated in the AGC loop each time
the AGC is initialized. This open loop pole location will directly
impact the closed loop pole locations as explained in the AGC
Mode section.
0x18 AGC B Average Samples
This 6-bit register contains the scale used for the CIC filter and
the number of power samples to be averaged before being fed to
the CIC filter.
Bits 5–2 define the scale used for the CIC filter.
Bits 1–0 define the number of samples to be averaged before
they are sent to the CIC decimating filter. This number can be
set between 1 and 4, with bit representation 00 meaning one
sample, and bit representation 11 meaning four samples.
0x19 AGC B Update Decimation
This 12-bit register sets the AGC decimation ratio from 1 to
4096. An appropriate scaling factor should be set factor to avoid
loss of bits.
0x1A Parallel Port Control A
Data is output through either a parallel port interface or a link
port interface. When 0x19 Bit 7 = 0, the use of Link Port A is
disabled and the use of Parallel Port A is enabled. The parallel
port provides different data modes for interfacing with DSPs
or FPGAs.
Bit 0 selects which data is output on Parallel Port A. When Bit 0
= 0, Parallel Port A outputs data from the RCF according to the
format specified by Bits 1–4. When Bit 0 = 1, Parallel Port A
outputs the data from the AGCs according to the format speci-
fied by Bits 1 and 2.
In AGC mode, Bit 0 = 1, and Bit 1 determines if Parallel Port A
is able to output data from AGC A and Bit 2 determines if
Parallel Port A is able to output data from AGC B. The order of
output depends on the rate of triggers from each AGC, which in
turn is determined by the decimation rate of the channels feed-
ing it. In Channel mode, Bit 0 = 0, and Bits 1–4 determine
which combination of the four processing channels is output.
The output order depends on the rate of triggers received from
each channel, which is determined by the decimation rate of
each channel. The channel output indicator pins can be used to
determine which data came from which channel.
Bit 5 determines the format of the output data words. When
Bit 5 = 0, Parallel Port A outputs 16-bit words on its 16-bit
bus. This means that I and Q data are interleaved, and the IQ
indicator pin determines whether data on the port is I data or Q
data. When Bit 5 = 1, Parallel Port A is outputting an 8-bit I
word and an 8-bit Q word at the same time, and the IQ indica-
tor pins will be high.
0x1B Link Port Control A
Data is output through either a parallel port interface or a link
port interface. The link port provides an efficient data link
between the AD6635 and a TigerSHARC DSP, and can be
enabled by setting Bit 7 = 1.
Bit 0 selects which data is output on Link Port A. When Bit 0 =
0, Link Port A outputs data from the RCF according to the
format specified by Bit 1. When Bit 0 = 1, Link Port A outputs
the data from the AGCs according to the format specified by
Bits 1 and 2.
Bit 1 has two different meanings that depend on whether data is
coming from the AGCs or from the RCFs. When data is coming
from the RCFs (Bit 0 = 0), Bit 1 selects between 2- and 4-channel
data mode. Bit 1 = 1 indicates that Link Port A transmits RCF
IQ words alternately from Channels 0 and 1. When Bit 1 = 1,
Link Port A outputs RCF IQ words from each of the four chan-
nels in succession: 0, 1, 2, then 3. However, when AGC data is
selected (Bit 0 = 1), Bit 1 selects the AGC data output mode.
In this mode, when Bit 1 = 1, Link Port A outputs AGC A IQ
and RSSI words. In this mode, RSSI words must be included
by setting Bit 2 = 0. However, if Bit 0 = Bit 1 = 0, AGC A and
B are alternately output on Link Port A, and the inclusion or
exclusion of the RSSI words is determined by Bit 2.
Bit 2 selects if RSSI words are included or not in the data out-
put. If Bit 1 = 1, Bit 2 = 0. Since the RSSI words are only two
bytes long (12 bits appended with four zeros) and the IQ words
are four bytes long, the RSSI words are padded with zeros to
give a full 16-byte TigerSHARC quad-word. If AGC output is
not selected (Bit 0 = 0), then this bit can be any value.
Bits 6–3 specify the programmable delay value for Link Port A
between the time the link port receives a data ready from the
receiver and the time it transmits the first data-word. The link
port must wait at least six cycles of the receiver’s clock, so this
value allows the user to use clocks of differing frequency and
phase for the AD6635 link port and the TigerSHARC link port.
There is more information on the limitations and relationship of
these clocks in the Link Ports section.
0x1C Parallel Port Control B
Data is output through either a parallel port interface or a link
port interface. When 0x1D Bit 7 = 0, the use of Link Port B is
disabled and the use of Parallel Port B is enabled. The parallel
port provides different data modes for interfacing with DSPs or
FPGAs.
Bit 0 selects which data is output on Parallel Port B. When Bit
0 = 0, Parallel Port B outputs data from the RCF according to
the format specified by Bits 1–4. When Bit 0 = 1, Parallel Port B
outputs the data from the AGCs according to the format speci-
fied by Bits 1 and 2.
In AGC mode, Bit 0 = 1, and Bit 1 determines if Parallel Port B
is able to output data from AGC A, and Bit 2 determines if
Parallel Port B is able to output data from AGC B. The order of
output depends on the rate of triggers from each AGC, which in
turn is determined by the decimation rate of the channels feed-
ing it. In Channel mode, Bit 0 = 0, and Bits 1–4 determine
which combination of the four processing channels is output.
The output order depends on the rate of triggers received from
each channel, which is determined by the decimation rate of
each channel. The channel output indicator pins can be used to
determine which data came from which channel.
Bit 5 determines the format of the output data words. When
Bit 5 = 0, Parallel Port B outputs 16-bit words on its 16-bit
bus.
This means that I and Q data are interleaved, and the IQ
indicator pin determines whether data on the port is I data or Q
data. When Bit 5 = 1, Parallel Port B is outputting an 8-bit I
word and an 8-bit Q word at the same time, and the IQ indica-
tor pins will be high.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD6635BB/PCB 制造商:Analog Devices 功能描述:Evaluation Kit For 4-Channel, 80MSPS WCDMA Receive Signal Processor
AD6635BBZ 制造商:Analog Devices 功能描述:Receive Signal Processor 324-Pin BGA
AD6636 制造商:AD 制造商全稱:Analog Devices 功能描述:150 MSPS Wideband Digital Down-Converter (DDC)
AD6636BBC 制造商:Analog Devices 功能描述:Digital Down Converter 256-Pin CSP-BGA
AD6636BBCZ 功能描述:IC DIGITAL DWNCONV 6CH 256CSPBGA RoHS:是 類別:RF/IF 和 RFID >> RF 混頻器 系列:AD6636 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:100 系列:- RF 型:W-CDMA 頻率:2.11GHz ~ 2.17GHz 混頻器數(shù)目:1 增益:17dB 噪音數(shù)據(jù):2.2dB 次要屬性:- 電流 - 電源:11.7mA 電源電壓:2.7 V ~ 3.3 V 包裝:托盤 封裝/外殼:12-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:12-QFN-EP（3x3）
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