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參數(shù)資料
| 型號： | AD6635BB |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 無繩電話/電話 |
| 英文描述： | 4-Channel, 80 MSPS WCDMA Receive Signal Processor (RSP) |
| 中文描述： | TELECOM, CELLULAR, BASEBAND CIRCUIT, PBGA324 |
| 封裝： | 19 X 19 MM, PLASTIC, BGA-324 |
| 文件頁數(shù)： | 43/60頁 |
| 文件大?。?/td> | 799K |
| 代理商： | AD6635BB |
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REV. 0
AD6635
–43–
When these bits are 00 the input sample rate (f
SAMP
) of the
channel is equal to the rate of the high speed CLK signal. When
IEN is low, the data going into the channel is masked to 0. This
is an appropriate mode for TDD systems in which the receiver
may wish to mask off the transmitted data yet still remain in the
proper phase for the next receive burst.
When these bits are 01, the input sample rate is determined by
the fraction of the rising edges of CLK on which the IEN input
is high. For example, if IEN toggles on every rising edge of
CLK, then the IEN signal will only be sampled high on one out
of every two rising edges of CLK. This means that the input
sample rate f
SAMP
will be one-half the CLK rate.
When these bits are 10, the input sample rate is determined by
the rate at which the IEN pin toggles. The data that is captured
on the rising edge of CLK after IEN transitions from low to
high is processed. When these bits are 11, the accumulator and
sample CLK are determined by the rate at which the IEN pin
toggles. The data that is captured on the rising edge of CLK
after IEN transitions from high to low is processed. For
example, control modes 10 and 11 can be used to allow
interleaved data from either the A or B input ports and then
assigned to the respective channel. The IEN pin selects the data
Table XI. Channel Memory Map (Part 2)
Channel Address
Register
Bit Width
Comments
90
91
92
rCIC2 Decimation – 1
rCIC2 Interpolation – 1
rCIC2 Scale
12
9
12
MrCIC2 – 1
LrCIC2 – 1
11: Exponent Invert
10: Exponent Weight
9–5: rCIC2_QUIET[4:0]
4–0: rCIC2_LOUD[4:0]
Reserved (Must Be Written Low)
MCIC5 – 1
4–0: CIC5_SCALE[4:0]
Reserved (Must Be Written Low)
93
94
95
96
97–9F
A0
A1
A2
A3
A4
Reserved
CIC5 Decimation – 1
CIC5 Scale
Reserved
Unused
RCF Decimation – 1
RCF Decimation Phase
RCF Number of Taps – 1
RCF Coefficient Offset
RCF Control Register
8
8
5
8
8
8
8
8
11
MRCF – 1
P
RCF
NTaps – 1
CO
RCF
or RCF
OFF
10: RCF Bypass BIST
9: RCF Input Select (Own 0, Other 1)
8: Program RAM Bank 1/0
7: Use Common Exponent
6: Force Output Scale
5–4: Output Format
1x: Floating Point 12 + 4
01: Floating Point 8 + 4
00: Fixed Point
3–0: Output Scale
such that one channel could be configured in Mode 10 and
another could be configured in Mode 11.
Bit 3 determines whether the phase accumulator of the NCO is
cleared when a hop occurs. The hop can originate from either
the Pin_SYNC or Soft_SYNC. When this bit is set to 0, the hop
is phase continuous and the accumulator is not cleared. When
this bit is set to 1, the accumulator is cleared to 0 before it
begins accumulating the new frequency word. This is appropriate
when multiple channels are hopping from different frequencies
to a common frequency.
Bits 2–1 control whether the dithers of the NCO are acti-
vated. The use of these features is heavily determined by the
system constraints. Consult the numerically controlled
oscillator (NCO) section for more detailed information on
the
use of dither.
Bit 0 of this register allows the NCO frequency translation
stage to be bypassed. When this occurs, the data from the A
input port is passed down the I path of the channel and the
data from the B input port is passed down the Q path of the
channel. This allows a real filter to be performed on baseband
I and Q data. For Channels 4 to 7, C input port is I-path and
D input port is Q-path.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD6635BB/PCB | 制造商:Analog Devices 功能描述:Evaluation Kit For 4-Channel, 80MSPS WCDMA Receive Signal Processor |
| AD6635BBZ | 制造商:Analog Devices 功能描述:Receive Signal Processor 324-Pin BGA |
| AD6636 | 制造商:AD 制造商全稱:Analog Devices 功能描述:150 MSPS Wideband Digital Down-Converter (DDC) |
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| AD6636BBCZ | 功能描述:IC DIGITAL DWNCONV 6CH 256CSPBGA RoHS:是 類別:RF/IF 和 RFID >> RF 混頻器 系列:AD6636 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:100 系列:- RF 型:W-CDMA 頻率:2.11GHz ~ 2.17GHz 混頻器數(shù)目:1 增益:17dB 噪音數(shù)據(jù):2.2dB 次要屬性:- 電流 - 電源:11.7mA 電源電壓:2.7 V ~ 3.3 V 包裝:托盤 封裝/外殼:12-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:12-QFN-EP（3x3） |
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