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參數資料
| 型號： | AD6636CBCZ1 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 數字上／下變頻 |
| 英文描述： | 150 MSPS Wideband Digital Down-Converter (DDC) |
| 中文描述： | 150MSPS的寬帶數字下變頻器（DDC） |
| 文件頁數： | 25/72頁 |
| 文件大?。?/td> | 1629K |
| 代理商： | AD6636CBCZ1 |
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AD6636
Rev. 0 | Page 25 of 72
Table 11. Correction Control Registers
Register
I/Q Correction Control
Bits
15–12
11–8
7–4
3
2
Decription
Amplitude Loop BW
Phase Loop BW
DC Loop BW
Reserved (Logic 0)
Amplitude Correction
Enable
Phase Correction Enable
DC Correction Enable
DC Offset Q
DC Offset I
Amplitude Correction
DC Offset Correction I
DC Offset Correction Q
Amplitude Offset
Correction
Phase Offset Correction
1
0
31–16
15–0
31–16
15–0
Phase Correction
DC Correction
All ADCs have a nominal dc offset related to them. If the ADCs
in the I and Q path have different dc offsets due to variations in
manufacturing process, the dc correction circuit can be used to
compensate for these dc offsets. Writing Logic 1 into the dc
correction enable bit of the AB (or CD) correction control
register enables the dc correction block. Two dc estimation
blocks are used, one each for the I and Q paths. The estimated
dc value is subtracted from the I and Q paths. Therefore, the dc
signal is removed independently from the I and Q path signals.
A cascade of two low-pass decimating filters estimates the dc
offset in the feedback loop. A decimating first-order CIC filter is
followed by an interpolating second-order CIC filter. The
decimation and interpolation values of the CIC filters are the
same and are programmable between 2
12
and 2
24
in powers of 2.
The 4-bit dc loop BW word in the I/Q correction control AB (or
CD) register is used to program this decimation (interpolation)
value. When the dc loop BW is a 0, decimation is 2
12
, and when
the dc loop BW is 11, decimation is 2
24
.
When the dc correction circuit is enabled, the dc correction
values are estimated. The values, which are estimated independ-
ently in the I and Q paths, are subtracted independently from
their respective datapaths. These dc correction values are also
available for output continuously through the dc correction I
and dc correction Q registers. These registers contain register
16-bit dc offset values whose MSB-justified values are
subtracted directly from MSB-justified ADC inputs for the I
and Q paths.
When the dc correction circuit is disabled, the value in the dc
correction register is used for continuously subtracting the dc
offset from I and Q datapaths. This method can be used to
manually set the dc offset instead of using the automatic dc
correction circuit.
Phase Correction
When using complex ADC input, the I and Q datapaths
typically have phase offset, caused mainly by the local oscillator
and demodulator IC. The AD6636 phase-offset correction
circuit can be used to compensate for this phase offset.
When the phase correction enable bit is Logic 1, the phase error
between I and Q is estimated (ideally, the phase should be 90°).
The phase mismatch is estimated over a period of time
determined by the integrator loop bandwidth. This integrator is
implemented as a first-order CIC decimating filter, whose
decimation value can vary between 2
12
and 2
24
in powers of 2.
Phase loop BW (Bits [11:8]) of the I/Q correction control
register determine this decimation value. When phase loop BW
equals 0, the decimation value is 2
12
, and when phase loop BW is
11, the decimation value is 2
24
.
While the phase offset correction circuit is enabled, the
tan(phase_mismatch) is estimated continuously. This value is
multiplied with Q path data and added to I path data
continuously. The estimated value is also updated in the phase
offset correction register. The tan(phase_mismatch) can be
±0.125 with a 14-bit resolution. This converts to a phase
mismatch of about ±7.125°.
When the phase offset correction circuit is disabled, the value in
the phase correction register multiplied with the Q path data
and added to the I path data continuously. This method can be
used to manually set the phase offset instead of using the
automatic phase offset correction circuit.
Amplitude Correction
When using complex ADC input, the I and Q datapaths
typically have amplitude offset, caused mainly by the local
oscillator and the demodulator IC. The AD6636 amplitude
offset correction circuit can be used to compensate for this
amplitude offset.
When the amplitude correction enable bit is Logic 1, the
amplitude error between the I and Q datapaths is estimated. The
amplitude mismatch is estimated over a period of time
determined by the integrator loop bandwidth. This integrator is
implemented as a first-order CIC decimating filter, whose
decimation value can vary between 2
12
and 2
24
in powers of 2.
Phase loop BW (Bits [11:8]) of the I/Q correction control
register determines this decimation value. When the phase loop
BW equals 0, the decimation value is 2
12
, and when phase loop
BW is 11, the decimation value is 2
24
.
While the amplitude offset correction circuit is enabled, the
difference (MAG(Q) – MAG(I)) is estimated continuously. This
value is multiplied with the Q path data and added to the Q
path data continuously. The estimated value is also updated in
the phase offset correction register. The difference (MAG(Q) –
MAG(I)) can be between 1.125 and 0.875 with a 14-bit
resolution.
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