參數(shù)資料
型號： AD6636CBCZ1
廠商： Analog Devices, Inc.
元件分類： 數(shù)字上／下變頻
英文描述： 150 MSPS Wideband Digital Down-Converter (DDC)
中文描述： 150MSPS的寬帶數(shù)字下變頻器（DDC）
文件頁數(shù)： 29/72頁
文件大小： 1629K
代理商： AD6636CBCZ1
AD6636
Table 13 can be used to decide the minimum decimation
required in the CIC stage to preserve a certain bandwidth. The
CIC5 stage can protect a much wider bandwidth to any given
rejection, when a decimation ratio lower than that identified in
the table is used. The table helps to calculate an upper boundary
on decimation, M
CIC
, given the desired filter characteristics.
Rev. 0 | Page 29 of 72
Table 13. SSB CIC5 Alias Rejection Table (f
in
= 1)
MCIC5
60 dB
70 dB
2
8.078
6.393
3
6.367
5.11
4
5.022
4.057
5
4.107
3.326
6
3.463
2.808
7
2.989
2.425
8
2.627
2.133
9
2.342
1.902
10
2.113
1.716
11
1.924
1.563
12
1.765
1.435
13
1.631
1.326
14
1.516
1.232
15
1.416
1.151
16
1.328
1.079
17
1.25
1.016
18
1.181
0.96
19
1.119
0.91
20
1.064
0.865
21
1.013
0.824
22
0.967
0.786
23
0.925
0.752
24
0.887
0.721
25
0.852
0.692
26
0.819
0.666
27
0.789
0.641
28
0.761
0.618
29
0.734
0.597
30
0.71
0.577
31
0.687
0.559
32
0.666
0.541
80 dB
5.066
4.107
3.271
2.687
2.27
1.962
1.726
1.54
1.39
1.266
1.162
1.074
0.998
0.932
0.874
0.823
0.778
0.737
0.701
0.667
0.637
0.61
0.584
0.561
0.54
0.52
0.501
0.484
0.468
0.453
0.439
90 dB
4.008
3.297
2.636
2.17
1.836
1.588
1.397
1.247
1.125
1.025
0.941
0.87
0.809
0.755
0.708
0.667
0.63
0.597
0.568
0.541
0.516
0.494
0.474
0.455
0.437
0.421
0.406
0.392
0.379
0.367
0.355
100 dB
3.183
2.642
2.121
1.748
1.48
1.281
1.128
1.007
0.909
0.828
0.76
0.703
0.653
0.61
0.572
0.539
0.509
0.483
0.459
0.437
0.417
0.399
0.383
0.367
0.353
0.34
0.328
0.317
0.306
0.297
0.287
Example Calculations
Goal:
Implement a filter with an input sample rate of 100 MHz
requiring 100 dB of alias rejection for a ± 1.4 MHz pass band.
Solution:
First determine the percentage of the sample rate that
is represented by the pass band.
4
=
MHz
100
MHz
4
100
×
=
fraction
BW
In the 100 dB column in Table 13, find the value greater than
or equal to the pass-band percentage of the clock rate. Then
find the corresponding rate decimation factor (M
CIC
). For an
M
CIC
of 6, the frequency that has 100 dB of alias rejection is
1.48%, which is slightly larger than the 1.4% calculated.
Therefore, for this example, the maximum bound on CIC
decimation rate is 6. A higher M
CIC
means less alias rejection
than the 100 dB required.
FIR HALF-BAND BLOCK
The output of the CIC filter is pipelined into the FIR HB (half-
band) block. Each channel has two sets of cascading fixed-
coefficient FIR and fixed-coefficient half-band filters. The half-
band filters decimate by 2. Each of these filters (FIR1, HB1,
FIR2, HB2) are described in the following sections.
3-Tap Fixed-Coefficient Filter (FIR1)
The 3-tap FIR filter is useful in certain filter configurations in
which extra alias protection is needed for the decimating HB1
filter. It is a simple sum-of-products FIR filter with three filter
taps and 2-bit fixed coefficients. Note that this filter does not
decimate. The coefficients of this symmetric filter are {1, 2, 1}.
The normalized coefficients used in the implementation are
{0.25, 0.5, 0.25}.
The user can either use or bypass this filter. Writing Logic 0 to
the FIR1 enable bit in the FIR-HB control register bypasses this
fixed-coefficient filter. The filter is useful only in certain filter
configurations and bypassing it for other applications results in
power savings.
0
FRACTION OF FIR1 INPUT SAMPLE RATE
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
d
0
–16.67
–8.33
–33.33
–25.00
–50.00
–41.67
–66.67
–58.33
–83.33
–75.00
–100.00
–91.67
0.34
0.66
–81
FIR1 RESPONSE
Figure 31. FIR1 Filter Response to the Input Rate of the Filter
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