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參數(shù)資料
| 型號(hào)： | AD6636CBCZ1 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 數(shù)字上／下變頻 |
| 英文描述： | 150 MSPS Wideband Digital Down-Converter (DDC) |
| 中文描述： | 150MSPS的寬帶數(shù)字下變頻器（DDC） |
| 文件頁數(shù)： | 63/72頁 |
| 文件大?。?/td> | 1629K |
| 代理商： | AD6636CBCZ1 |
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AD6636
<6:5>: NCO Sync Hop Select Bits. These bits determine which
SYNC input pin is used by this channel for a hop synchroniza-
tion operation. Table 35 describes the selection.
Rev. 0 | Page 63 of 72
Table 35. Sync Hop Select Bits
NCO Control <6:5>
00
01
10
11
SYNC Pin Used for Hop Synchronization
SYNC0
SYNC1
SYNC2
SYNC3
<4>: This bit is open.
<3>: NCO Bypass Bit. When this bit is set, the NCO is bypassed
shuts down for power savings. This bit can be used for power
savings, when NCO frequency of dc or 0 Hz is required. When
this bit is cleared, the NCO operates as programmed.
<2>: Clear NCO Accumulator Bit. When this bit is set, the clear
NCO accumulator bit synchronously clears the phase accumu-
lator on all frequency hops in this channel. When this bit is
cleared, the accumulator is not cleared and phase continuous
hops are implemented.
<1>: Phase Dither Enable Bit. When this bit is set, phase
dithering in the NCO is enabled. When this bit is cleared, phase
dithering is disabled.
<0>: Amplitude Dither Enable Bit. When this bit is set,
amplitude dithering in the NCO is enabled. When this bit is
cleared, amplitude dithering is disabled.
Channel Start Hold-Off Counter <15:0>
When a start synchronization (software or hardware) occurs on
the channel, the value in this register is loaded into a down-
counter. When the counter has finished counting down to 0, the
channel operation is started.
NCO Frequency Hop Hold-Off Counter <15:0>
When a hop sync occurs, a counter is loaded with the NCO
frequency hold-off register value. The 16-bit counter starts
counting down. When it reaches 0, the new frequency value in
the shadow register is written to the NCO frequency register.
(See the Numerically Controlled Oscillator (NCO) section.)
NCO Frequency <31:0>
The value in this register is used to program the NCO tuning
frequency. The value to be programmed is given by the
following equation:
NCO Frequency Register
=
CLK
FREQUENCY
NCO
_
× 2
32
where:
NCO_FREQUENCY
is the desired NCO tuning frequency.
CLK
is the ADC clock rate.
The value given by the equation should be loaded into the
register in binary format.
NCO Phase Offset <15:0>
The value in the register is loaded into the phase accumulator of
the NCO block every time a start sync or hop sync is received
by the channel. This allows individual channels to be started
with a known nonzero phase. The NCO phase offset is not
loaded on a hop sync, if Bit <2> of the NCO control register
(clear phase accumulator on hop) is cleared. This NCO offset
register value is interpreted as a 16-bit unsigned integer. A
0x0000 in this register corresponds to a 0 radian offset, and a
0xFFFF corresponds to an offset of 2π (1 1/(2
16
)) radians.
CIC Bypass <0>
When this bit is set, the entire CIC filter is bypassed. The
output of CIC filter is driven straight from the input without
any change. When this bit is cleared, the CIC filter operates in
normal mode as programmed. Writing Logic 1 to this bit
disables both the CIC decimation operation and the CIC
scaling operation.
CIC Decimation <4:0>
This 5-bit word specifies the CIC filter decimation value minus
1. A value of 0x00 is a decimation of 1 (bypass), and 0x1F is a
decimation of 32. Writing a value of 0 in this register bypasses
CIC filtering, but does not bypass the CIC scaling operation.
CIC Scale Factor <4:0>
This 5-bit word specifies the CIC filter scale factor used to
compensate for the gain provided by the CIC filter. The
recommended value is given by the following equation:
CIC Scale Register
=
ceil
(5 × log
2
(
M
CIC
)) 5
where:
M
CIC
is the decimation rate of the CIC (one more than the value
in the CIC decimation register).
ceil
operation gives the closest integer greater than or equal to
the argument.
The valid range for this register is decimal 0 to 20.
FIR-HB Control <3:0>
<3>: FIR1 Enable Bit. When this bit is set, the FIR1 fixed-
coefficient filter is enabled. When cleared, FIR1 is bypassed.
<2>: HB1 Enable Bit. When this bit is set, the HB1 half-band
filter is enabled. When cleared, HB1 is bypassed.
<1>: FIR2 Enable Bit. When this bit is set, the FIR2 fixed-
coefficient filter is enabled. When cleared, FIR2 is bypassed.
<0>: HB2 Enable bit. When this bit is set, the HB2 half-band
filter is enabled. When cleared, HB2 is bypassed.
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