參數(shù)資料
型號： AD6636CBCZ1
廠商： Analog Devices, Inc.
元件分類： 數(shù)字上／下變頻
英文描述： 150 MSPS Wideband Digital Down-Converter (DDC)
中文描述： 150MSPS的寬帶數(shù)字下變頻器（DDC）
文件頁數(shù)： 45/72頁
文件大?。?/td> 1629K
代理商： AD6636CBCZ1
AD6636
Rev. 0 | Page 45 of 72
PxCH [2:0]
PCLKn
t
DPREQ
PxREQ
PxACK
t
DPP
I [15:8]
Q [7:0]
Px [15:0]
PxIQ
t
DPIQ
PxCH [2:0] =
AGC NO.
t
DPCH
PxGAIN
LOGIC LOW 0
0
Figure 42. Parallel I/Q Mode without an AGC Gain Word
When an output data sample is available for output from an
AGC, the parallel port initiates the transfer by pulling the
PxREQ signal high. In response, the processor receiving the
data needs to pull the PxACK signal high, acknowledging that it
is ready to receive the signal. In Figure 42, the PxACK is already
pulled high and, therefore, the 8-bit I data and 8-bit Q data are
simultaneously output on the data bus on the next PCLK rising
edge after PxREQ is driven logic high. The PxIQ signal also
goes high to indicate that I/Q data is available on the data bus.
When I/Q data is being output, the channel indicator pins
PxCH[2:0] indicate the data source (AGC number).
Figure 42 is the timing diagram for interleaved I/Q mode with
the AGC gain word disabled. Figure 43 is a similar timing
diagram with the AGC gain word enabled. I and Q data are as
shown in Figure 39. In the PCLK cycle after the I/Q data, the
AGC gain word is output on the data bus, and the PxGAIN
signal is pulled high to indicate that the gain word is available
on the parallel port. During this PCLK cycle, the PxIQ signal is
pulled low to indicate that I/Q data is not available on the data
bus. Therefore, in parallel I/Q mode, a minimum of two PCLK
cycles is required to output one sample of output data on the
parallel port without and with the AGC gain word, respectively.
The order of data output is dependent on when data arrives at
the port, which is a function of total decimation rate, DRCF/
CRCF decimation phase, and start hold-off values. Priority
order from highest to lowest is, AGCs 0, 1, 2, 3, 4, and 5 for both
parallel I/Q and interleaved modes of output.
Master/Slave PCLK Modes
The parallel ports can operate in either master or slave mode.
The mode is set via PCLK master mode bit in the Parallel Port
Control 2 register. The parallel ports power up in slave mode to
avoid possible contentions on the PCLK pin.
In master mode, PCLK is an output derived by dividing
PLL_CLK down by the PCLK divisor. The PCLK divisor can
have a value of 1, 2, 4, or 8, depending on the 2-bit PCLK divisor
word setting in the Parallel Port Control 2 register. The highest
PLCK rate in master mode is 200 MHz. Master mode is selected
by setting the PCLK master mode bit in the Parallel Port
Control 2 register.
divisor
PCLK
rate
CLK
PLL
rate
PCLK
_
=
In slave mode, external circuitry provides the PCLK signal.
Slave-mode PCLK signals can be either synchronous or
asynchronous. The maximum slave mode PCLK frequency is
also 200 MHz.
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參數(shù)描述
AD6636PCB 制造商:AD 制造商全稱:Analog Devices 功能描述:150 MSPS Wideband Digital Down-Converter (DDC)
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