參數(shù)資料
型號: AD6636CBCZ1
廠商: Analog Devices, Inc.
元件分類: 數(shù)字上/下變頻
英文描述: 150 MSPS Wideband Digital Down-Converter (DDC)
中文描述: 150MSPS的寬帶數(shù)字下變頻器(DDC)
文件頁數(shù): 69/72頁
文件大?。?/td> 1629K
代理商: AD6636CBCZ1
AD6636
AGC 0, I Output <15:0>
This read-only register provides the latest in-phase output
sample from AGC 0. Note that AGC 0 might be bypassed, and
that AGC 0 here is representative of the datapath only.
AGC 0, Q Output <15:0>
This read-only register provides the latest quadrature-phase
output sample from AGC 0. Note that AGC 0 might be
bypassed, and that AGC 0 here is representative of the
datapath only.
AGC 1, I Output <15:0>
This read-only register provides the latest in-phase output
sample from AGC 1. Note that AGC 1 might be bypassed and
that AGC 1 here is representative of the datapath only.
AGC 1, Q Output <15:0>
This read-only register provides the latest quadrature-phase
output sample from AGC 1. Note that AGC 1 might be bypassed
and that AGC 1 here is representative of the datapath only.
AGC 2, I Output <15:0:
This read-only register provides the latest in-phase output
sample from AGC 2. Note that AGC 2 might be bypassed and
that AGC 2 here is representative of the datapath only.
AGC 2, Q Output <15:0>
This read-only register provides the latest quadrature-phase
output sample from AGC 2. Note that AGC 2 might be bypassed
and that AGC 2 here is representative of the datapath only.
AGC 3, I Output <15:0>
This read-only register provides the latest in-phase output
sample from AGC 3. Note that AGC 3 might be bypassed and
that AGC 3 here is representative of the datapath only.
AGC 3, Q output <15:0>
This read-only register provides the latest quadrature-phase
output sample from AGC 3. Note that AGC 3 might be bypassed
and that AGC 3 here is representative of the datapath only.
AGC 4, I Output <15:0>
This read-only register provides the latest in-phase output
sample from AGC 4. Note that AGC 4 might be bypassed and
that AGC 4 here is representative of the datapath only.
Rev. 0 | Page 69 of 72
AGC 4, Q Output <15:0>
This read-only register provides the latest quadrature-phase
output sample from AGC 4. Note that AGC 4 might be bypassed
and that AGC 4 here is representative of the datapath only.
AGC 5, I Output <15:0>
This read-only register provides the latest in-phase output
sample from AGC 5. Note that AGC 5 might be bypassed and
that AGC 5 here is representative of the datapath only.
AGC 5, Q Output <15:0>
This read-only register provides the latest quadrature-phase
output sample from AGC 5. Note that AGC 5 might be bypassed
and that AGC 5 here is representative of the datapath only.
AGC 0, RSSI Output <11:0>
This read-only register provides the latest RSSI output sample
from AGC 0. This register is updated only when AGC 0 is
enabled and operating.
AGC 1, RSSI Output <11:0>
This read-only register provides the latest RSSI output sample
from AGC 1. This register is updated only when AGC 1 is
enabled and operating.
AGC 2, RSSI Output <11:0>
This read-only register provides the latest RSSI output sample
from AGC 2. This register is updated only when AGC 2 is
enabled and operating.
AGC 3, RSSI Output <11:0>
This read-only register provides the latest RSSI output sample
from AGC 3. This register is updated only when AGC 3 is
enabled and operating.
AGC 4, RSSI Output <11:0>
This read-only register provides the latest RSSI output sample
from AGC 4. This register is updated only when AGC 4 is
enabled and operating.
AGC 5, RSSI Output <11:0>
This read-only register provides the latest RSSI output sample
from AGC 5. This register is updated only when AGC 5 is
enabled and operating.
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