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AD6636
Maximum Number of Taps Calculated
The output rate of the DRCF filter is given by
Rev. 0 | Page 34 of 72
DRCF
MRCF
M
DRCF
f
f
=
where:
f
MRCF
is the data rate out of the MRCF filter and into the DRCF
filter.
M
DRCF
is the decimation rate in the DRCF filter.
The DRCF filter consists of two multipliers (one each for the
I and Q paths). Each multiplier, working at the high speed clock
rate (PLL clock), can do one multiply (or one tap) per high
speed clock cycle. Therefore, the maximum number of filter
taps that can be calculated (symmetrical or asymmetrical filter)
is given by
1
=
DRCF
PLLCLK
f
f
ceil
Taps
of
Number
Maximum
where:
f
PLLCLK
is the high speed internal processing clock generated by
the PLL clock multiplier.
f
DRCF
is the output rate of the DRCF filter calculated above.
Programming DRCF Registers for an Asymmetrical Filter
To program the DRCF registers for an asymmetrical filter:
1.
Write
NTAPS
– 1 in the DRCF taps register, where
NTAPS
is the number of filter taps. The absolute maximum value
for
NTAPS
is 64 in asymmetrical filter mode.
2.
Write 0 for the DRCF coefficient offset register.
3.
Write 0 for the symmetrical filter bit in the DRCF control
register.
4.
Write the start address for the coefficient RAM, typically
equal to the coefficient offset register in the DRCF start
address register.
5.
In the DRCF stop address register, write the stop address
for the coefficient RAM, typically equal to the following:
Coefficient Offset
+
NTAPS
1
6.
Write all coefficients in reverse order (start with last
coefficient) to the DRCF coefficient memory register. If in
8-bit microport mode or serial port mode, write the lower
byte of the memory register first and then the higher byte.
7.
After each write access to the DRCF coefficient memory
register, the internal RAM address is incremented starting
with the start address and ending with the stop address.
Note that each write or read access increments the internal
RAM address. Therefore, all coefficients should be read first
before reading them back. Also, for debugging purposes, each
RAM address can be written individually by making the start
address and stop addresses the same. Therefore, to program one
RAM location, the user writes the address of the RAM location
to both the start and stop address registers, and then writes the
coefficient memory register.
Programming DRCF Registers for a Symmetric Filter
To program the DRCF registers for a symmetrical filter:
1.
Write
NTAPS
– 1 in the DRCF taps register, where
NTAPS
is the number of filter taps. The absolute maximum value
for
NTAPS
is 128 in symmetric filter mode.
2.
Write
ceil
(64 –
NTAPS
/2) for the DRCF coefficient offset
register, where the
ceil
function takes the closest integer
greater than or equal to the argument.
3.
Write 1 for the symmetrical filter bit in the DRCF control
register.
4.
Write the start address for the coefficient RAM, typically
equal to coefficient offset register, in the DRCF start
address register.
5.
Write the stop address for the coefficient RAM, typically
equal to ceil(
NTAPS
/2) – 1, in the DRCF stop address
register.
6.
Write all coefficients to the DRCF coefficient memory
register, starting with the middle of the filter and working
towards the end of the filter. When coefficients are
numbered 0 to
NTAPS
– 1, the middle coefficient is given
by the coefficient number ceil(
NTAPS
/2). If in 8-bit
microport mode or serial port mode, write the lower byte
of the memory register first and then the higher byte. After
each write access to the DRCF coefficient memory register,
the internal RAM address is incremented starting with the
start address and ending with stop address.
Note that each write or read access increments the internal
RAM address. Therefore, all coefficients should be read first
before reading them back. Also, for debugging purposes, each
RAM address can be written individually by making the start
and stop addresses the same. Therefore, to program one RAM
location, the user writes the address of the RAM location to
both the start and stop address registers, and then writes the
coefficient memory register.