參數(shù)資料
型號： AD6636CBCZ1
廠商： Analog Devices, Inc.
元件分類： 數(shù)字上／下變頻
英文描述： 150 MSPS Wideband Digital Down-Converter (DDC)
中文描述： 150MSPS的寬帶數(shù)字下變頻器（DDC）
文件頁數(shù)： 46/72頁
文件大?。?/td> 1629K
代理商： AD6636CBCZ1
AD6636
Rev. 0 | Page 46 of 72
PCLK
t
DPREQ
PxREQ
PxACK
t
DPP
I [15:8]
Q [15:8]
Px [15:0]
PxIQ
t
DPIQ
PxCH [2:0]
PxCH [2:0] = CHANNEL #
t
DPCH
GAIN [11:0] +
0000
PxGAIN
t
DPGAIN
0
Figure 43. Parallel I/Q Mode with an AGC Gain Word
Parallel Port Pin Functions
Table 24 describes the functions of the pins used by the parallel ports.
Table 24. Parallel Port Pin Functions
Pin Name
I/O
PCLK
I/O
Function
PCLK can operate as a master or as a slave. This setting is dependent on the 1-bit PCLK master mode bit in the
Parallel Port Control 2 register. As an output (master mode), the maximum frequency is CLK/N, where CLK is
AD6636 clock and N is an integer divisor of 1, 2, 4, or 8. As an input (slave mode), it can be asynchronous or
synchronous relative to the AD6636 CLK. This pin powers up as an input to avoid possible contentions. Parallel
port output pins change on the rising edge of PCLK.
Active high output. Synchronous to PCLK. A logic high on this pin indicates that data is available to be shifted out
of the port. When an acknowledge signal is received, data starts shifting out and this pin remains high until all
pending data has been shifted out.
Active high asynchronous input. Applying a logic low on this pin inhibits parallel port data shifting. Applying a
logic high to this pin when REQ is high causes the parallel port to shift out data according to the programmed
data mode.
ACK is sampled on the rising edge of PCLK. Assuming that REQ is asserted, the latency from the assertion of ACK
to data appearing at the parallel port output is no more than 1.5 PCLK cycles. ACK can be held high continuously;
in this case, when data becomes available, shifting begins 1 PCLK cycle after the assertion of REQ (see Figure 40,
Figure 41, Figure 42, and Figure 43).
High whenever I data is present on the parallel port data bus; otherwise low. In parallel I/Q mode, both I data and
Q data are available at the same time and, therefore, the PxIQ signal is pulled high.
High whenever the AGC gain word is present on the parallel port data bus; otherwise low.
PAREQ, PBREQ,
PCREQ
O
PAACK, PBACK,
PCACK
I
PAIQ, PBIQ,
PCIQ
PAGAIN,
PBGAIN,
PCGAIN
PACH[2:0],
PBCH[2:0],
PCCH[2:0]
PADATA[15:0],
PBDATA[15:0],
PCDATA[15:0]
These pins identify data in both of the parallel port modes. The 3-bit value identifies the source of the data (AGC
number) on the parallel port when it is being shifted out.
Parallel output port data bus. Output format is twos complement. In parallel I/Q mode, 8-bit data is present; in
interleaved I/Q mode, 16-bit data is available.
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