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| 型號(hào)： | AD9852/PCBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 1/52頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD9852 |
| 設(shè)計(jì)資源： | AD9852 Eval Brd BOM AD9852 Schematic |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | AgileRF™ |
| 類型： | 合成器 |
| 適用于相關(guān)產(chǎn)品： | AD9852 |
| 相關(guān)產(chǎn)品： | AD9852ASVZ-ND - IC DDS SYNTHESIZER CMOS 80-TQFP AD9852ASTZ-ND - IC DDS SYNTHESIZER CMOS 80-LQFP |
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CMOS 300 MSPS Complete DDS
AD9852
Rev. E
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityis assumedbyAnalogDevicesforitsuse,norforanyinfringements of patents or other
rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
2002–2007 Analog Devices, Inc. All rights reserved.
FEATURES
300 MHz internal clock rate
FSK, BPSK, PSK, chirp, AM operation
Dual integrated 12-bit D/A converters
Ultrahigh speed comparator, 3 ps rms jitter
Excellent dynamic performance
80 dB SFDR at 100 MHz (±1 MHz) AOUT
4× to 20× programmable reference clock multiplier
Dual 48-bit programmable frequency registers
Dual 14-bit programmable phase offset registers
12-bit programmable amplitude modulation and on/off
output shaped keying function
Single-pin FSK and BPSK data interfaces
PSK capability via I/O interface
Linear or nonlinear FM chirp functions with single pin
frequency hold function
Frequency ramped FSK
<25 ps rms total jitter in clock generator mode
Automatic bidirectional frequency sweeping
Sin(x)/x correction
Simplified control interface
10 MHz serial 2-wire or 3-wire SPI-compatible
100 MHz parallel 8-bit programming
3.3 V single supply
Multiple power-down functions
Single-ended or differential input reference clock
Small, 80-lead LQFP or TQFP with exposed pad
APPLICATIONS
Agile LO frequency synthesis
Programmable clock generator
FM chirp source for radar and scanning systems
Test and measurement equipment
Commercial and amateur RF exciter
FUNCTIONAL BLOCK DIAGRAM
DIGITAL MULTIPLIERS
SYSTEM
CLOCK
DAC RSET
INV
SINC
FILTER
FRE
Q
UE
NCY
ACCUMULATOR
ACC
1
I/O PORT BUFFERS
COMPARATOR
PROGRAMMING REGISTERS
4
× TO 20×
REFCLK
MULTIPLIER
DIFF/SINGLE
SELECT
REFERENCE
CLOCK IN
FSK/BPSK/HOLD
DATA IN
BIDIRECTIONAL
INTERNAL/EXTERNAL
I/O UPDATE CLOCK
READ
WRITE
SERIAL/
PARALLEL
SELECT
6-BIT ADDRESS
OR SERIAL
PROGRAMMING
LINES
8-BIT
PARALLEL
LOAD
MASTER
RESET
+VS
GND
CLOCK
OUT
ANALOG
IN
OSK
ANALOG
OUT
ANALOG
OUT
INTERNAL
PROGRAMMABLE
UPDATE CLOCK
PH
A
SE-
TO-
AMP
L
ITUDE
CONV
E
R
TE
R
PROGRAMMABLE
AMPLITUDE AND
RATE CONTROL
D
Q
CLK
÷2
INT
EXT
SYSTEM
CLOCK
REFCLK
BUFFER
SYSTEM
CLOCK
MUX
DELTA
FREQUENCY
RATE TIMER
SYSTEM
CLOCK
DELTA
FREQUENCY
WORD
FREQUENCY
TUNING
WORD 1
FREQUENCY
TUNING
WORD 2
FIRST 14-BIT
PHASE/OFFSET
WORD
SECOND 14-BIT
PHASE/OFFSET
WORD
AM
MODULATION
12-BIT DC
CONTROL
MUX
SYSTEM CLOCK
P
HAS
E
ACCUMULATOR
ACC
2
DDS CORE
12-BIT
COSINE
DAC
12-BIT
CONTROL
DAC
I
Q
12
MUX
SYSTEM
CLOCK
SYSTEM
CLOCK
48
14
BUS
12
14
17
48
AD9852
MODE SELECT
2
3
DE
MUX
00634-001
Figure 1.
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