參數(shù)資料
型號： AD9852/PCBZ
廠商： Analog Devices Inc
文件頁數(shù)： 6/52頁
文件大小： 0K
描述： BOARD EVAL FOR AD9852
設計資源： AD9852 Eval Brd BOM
AD9852 Schematic
標準包裝： 1
系列： AgileRF™
類型： 合成器
適用于相關(guān)產(chǎn)品： AD9852
相關(guān)產(chǎn)品： AD9852ASVZ-ND - IC DDS SYNTHESIZER CMOS 80-TQFP
AD9852ASTZ-ND - IC DDS SYNTHESIZER CMOS 80-LQFP
AD9852
Rev. E | Page 14 of 52
Figure 18 and Figure 19 show the residual phase noise performance of the AD9852 when operating with a 300 MHz reference clock with
the REFCLK multiplier bypassed vs. a 30 MHz reference clock with the REFCLK multiplier enabled at 10×.
0
CENTER 112.469MHz
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
50kHz/
SPAN 500kHz
00634-016
Figure 16. A Slight Change in Tuning Word Yields Dramatically Better Results;
112.469 MHz with All Spurs Shifted Out-of-Band, 300 MHz REFCLK
0
CENTER 39.1MHz
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
5kHz/
SPAN 50kHz
00634-017
Figure 17. Narrow-Band SFDR, 39.1 MHz, 50 kHz BW,
200 MHz REFCLK with REFCLK Multiplier Bypassed
FREQUENCY (Hz)
–100
–110
–150
–120
–130
–140
–160
–170
10
1M
100
100k
10k
1k
PH
A
SE
N
OISE
(
d
B
c
/H
z)
AOUT = 80MHz
AOUT = 5MHz
00634-018
Figure 18. Residual Phase Noise,
300 MHz REFCLK with REFCLK Multiplier Bypassed
FREQUENCY (Hz)
–90
–100
–140
–110
–120
–130
–150
–160
10
1M
100
100k
10k
1k
P
HAS
E
NOIS
E
(dBc
/Hz)
AOUT = 80MHz
AOUT = 5MHz
00634-019
Figure 19. Residual Phase Noise,
30 MHz REFCLK with REFCLK Multiplier = 10×
DAC CURRENT (mA)
55
0
S
F
DR
(dBc
)
54
53
52
51
50
49
48
5
1015
2025
00634-020
Figure 20. SFDR vs. DAC Current, 59.1 AOUT,
300 MHz REFCLK with REFCLK Multiplier Bypassed
FREQUENCY (MHz)
620
0
S
U
P
L
Y
CURRE
NT
(mA)
615
610
605
600
595
590
20
40
60
80
100
120
140
00634-021
Figure 21. Supply Current vs. Output Frequency (Variation Is Minimal,
Expressed as a Percentage, and Heavily Dependent on Tuning Word)
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