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| 型號： | AD9852/PCBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 16/52頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD9852 |
| 設(shè)計資源： | AD9852 Eval Brd BOM AD9852 Schematic |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | AgileRF™ |
| 類型： | 合成器 |
| 適用于相關(guān)產(chǎn)品： | AD9852 |
| 相關(guān)產(chǎn)品： | AD9852ASVZ-ND - IC DDS SYNTHESIZER CMOS 80-TQFP AD9852ASTZ-ND - IC DDS SYNTHESIZER CMOS 80-LQFP |
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AD9852
Rev. E | Page 23 of 52
OUT
ADDER
CLR ACC2
CLR ACC1
HOLD
00634-040
PHASE
ACCUMULATOR
SYSTEM
CLOCK
FREQUENCY
TUNING
WORD 1
20-BIT
RAMP RATE
CLOCK
48-BIT DELTA
FREQUENCY
WORD (TWOS
COMPLEMENT)
FREQUENCY
ACCUMULATOR
Figure 40. FM Chirp Components
F1
0
FREQUENCY
010 (RAMPED FSK)
F1
000 (DEFAULT)
0
MODE
TW1
DFW
RAMP RATE
I/O UD CLK
00634-041
Figure 41. Example of a Nonlinear Chirp
Basic FM Chirp Programming Steps
1.
Program a start frequency into Frequency Tuning Word 1
(Parallel Register Address 4 hex to Parallel Register
Address 9 hex), hereafter called FTW1.
2.
Program the frequency step resolution into the 48-bit, twos
complement delta frequency word (Parallel Register
Address 10 hex to Parallel Register Address 15 hex).
3.
Program the rate of change (time at each frequency) into
the 20-bit ramp rate clock (Parallel Register Address 1A hex
to Parallel Register Address 1C hex).
When programming is complete, an I/O update pulse at Pin 20
engages the program commands.
The necessity for a twos complement delta frequency word is to
define the direction in which the FM chirp moves. If the 48-bit
delta frequency word is negative (MSB is high), the incremental
frequency changes are in a negative direction from FTW1. If the
48-bit word is positive (MSB is low), the incremental frequency
changes are in a positive direction from FTW1.
It is important to note that FTW1 is only a starting point for
FM chirp. There is no built-in restraint requiring a return to
FTW1. Once the FM chirp begins, it is free to move (under
program control) within the Nyquist bandwidth (dc to one-half
the system clock). However, instant return to FTW1 can be
easily achieved.
Two control bits (CLR ACC1 and CLR ACC2) are available in the
FM chirp mode that allow the device to return to the beginning
frequency, FTW1, or to 0 Hz. When the CLR ACC1 bit (Register
Address 1F hex) is set high, the 48-bit frequency accumulator
(ACC1) output is cleared with a retriggerable one-shot pulse of
one system clock duration. The 48-bit delta frequency word input
to the accumulator is unaffected by the CLR ACC1 bit. If the
CLR ACC1 bit is held high, a one-shot pulse is delivered to the
frequency accumulator (ACC1) on every rising edge of the I/O
update clock. The effect is to interrupt the current chirp, reset the
frequency to that programmed into FTW1, and continue the chirp
at the previously programmed rate and direction. Figure 42 shows
clearing of the frequency accumulator output in chirp mode.
Shown in the diagram is the I/O update clock, which is either user
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