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| 型號： | AD9852/PCBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 52/52頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD9852 |
| 設(shè)計(jì)資源： | AD9852 Eval Brd BOM AD9852 Schematic |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | AgileRF™ |
| 類型： | 合成器 |
| 適用于相關(guān)產(chǎn)品： | AD9852 |
| 相關(guān)產(chǎn)品： | AD9852ASVZ-ND - IC DDS SYNTHESIZER CMOS 80-TQFP AD9852ASTZ-ND - IC DDS SYNTHESIZER CMOS 80-LQFP |
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AD9852
Rev. E | Page 9 of 52
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
2
D6
3
D5
4
D4
7
D1
6
D2
5
D3
1
D7
8
D0
9
DVDD
10
DVDD
12
DGND
13
NC
14
A5
15
A4
16
A3
17
A2/IO RESET
18
A1/SDO
19
A0/SDIO
20
I/O UD CLK
11
DGND
59
58
57
54
55
56
60
53
52
AGND
NC
AVDD
DACBP
DAC RSET
AVDD
AGND
IOUT2
51
IOUT2
49
IOUT1
48
IOUT1
47
AGND
46
AGND
45
AGND
44
AVDD
43
VINN
42
VINP
41
AGND
50
AVDD
NC = NO CONNECT
21
WR/
S
CLK
22
RD/CS
23
DV
DD
24
DV
DD
25
DV
DD
26
DGND
27
DGND
28
DGND
29
FS
K/BP
S
K
/HOLD
30
OSK
31
AV
DD
32
AV
DD
33
AGND
34
AGND
35
NC
36
VOU
T
37
AV
DD
38
AV
DD
39
AGND
40
AGND
80
DV
DD
79
DV
DD
78
DGND
77
DGND
76
DGND
75
DGND
74
DV
DD
73
DV
DD
72
DGND
71
M
A
STER
R
ESET
70
S/P
SELEC
T
69
REFCLK
68
REFCLK
67
AGND
66
AGND
65
AV
DD
64
DIFF
CLK
E
NABLE
63
NC
62
AGND
61
PLL
FILTER
PIN 1
AD9852
TOP VIEW
(Not to Scale)
00634-002
Figure 2. Pin Configuration
Table 5. Pin Function Descriptions
Pin Number
Mnemonic
Description
1 to 8
D7 to D0
8-Bit Bidirectional Parallel Programming Data Inputs. Used only in parallel programming mode.
9, 10, 23, 24, 25,
73, 74, 79, 80
DVDD
Connections for the Digital Circuitry Supply Voltage. Nominally 3.3 V more positive than AGND
and DGND.
11, 12, 26, 27, 28,
72, 75 to 78
DGND
Connections for Digital Circuitry Ground Return. Same potential as AGND.
13, 35, 57, 58, 63
NC
No Internal Connection.
14 to 16
A5 to A3
Parallel Address Inputs for Program Registers (Part of 6-Bit Parallel Address Inputs for Program
Register, A5:A0). Used only in parallel programming mode.
17
A2/IO RESET
Parallel Address Input for Program Registers (Part of 6-Bit Parallel Address Inputs for Program
Register, A5:A0)/IO Reset. A2 is used only in parallel programming mode. IO RESET is used when
the serial programming mode is selected, allowing an IO RESET of the serial communication bus
that is unresponsive due to improper programming protocol. Resetting the serial bus in this
manner does not affect previous programming, nor does it invoke the default programming
values seen in Table 9. Active high.
18
A1/SDO
Parallel Address Input for Program Registers (Part of 6-Bit Parallel Address Inputs for Program
Register, A5:A0)/Unidirectional Serial Data Output. A1 is used only in parallel programming
mode. SDO is used in 3-wire serial communication mode when the serial programming mode is
selected.
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