- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄18714 > AD9852/PCBZ (Analog Devices Inc)BOARD EVAL FOR AD9852 PDF資料下載
參數(shù)資料
| 型號： | AD9852/PCBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 15/52頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD9852 |
| 設(shè)計資源： | AD9852 Eval Brd BOM AD9852 Schematic |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | AgileRF™ |
| 類型： | 合成器 |
| 適用于相關(guān)產(chǎn)品： | AD9852 |
| 相關(guān)產(chǎn)品： | AD9852ASVZ-ND - IC DDS SYNTHESIZER CMOS 80-TQFP AD9852ASTZ-ND - IC DDS SYNTHESIZER CMOS 80-LQFP |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁當(dāng)前第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁
AD9852
Rev. E | Page 22 of 52
Additional flexibility in the ramped FSK mode is provided by
the AD9852’s ability to respond to changes in the 48-bit delta
frequency word and/or the 20-bit ramp rate counter at any time
during the ramping from F1 to F2 or vice versa. To create these
nonlinear frequency changes, it is necessary to combine several
linear ramps with different slopes in a piecewise fashion. This is
done by programming and executing a linear ramp at a rate or
slope and then altering the slope (by changing the ramp rate
clock or delta frequency word, or both). Changes in slope can
be made as often as needed before the destination frequency has
been reached to form the desired nonlinear frequency sweep
response. These piecewise changes can be precisely timed using
the 32-bit internal update clock (see the Internal and External
Update Clock section).
Nonlinear ramped FSK has the appearance of the chirp function
shown in Figure 41. The major difference between a ramped
FSK function and a chirp function is that FSK is limited to
operation between F1 and F2, whereas chirp operation has no
F2 limit frequency.
Two additional control bits (CLR ACC1 and CLR ACC2) are
available in the ramped FSK mode that allow more options. Setting
CLR ACC1 (Register Address 1F hex) high clears the 48-bit
frequency accumulator (ACC1) output with a retriggerable
one-shot pulse of one system clock duration. If the CLR ACC1
bit is left high, a one-shot pulse is delivered on the rising edge of
every update clock. The effect is to interrupt the current ramp,
reset the frequency to the start point (F1 or F2), and then
continue to ramp up (or down) at the previous rate. This occurs
even when a static F1 or F2 destination frequency has been
achieved.
Alternatively, the CLR ACC2 control bit (Register Address 1F hex)
can be used to clear both the frequency accumulator (ACC1)
and the phase accumulator (ACC2). When this bit is set high,
the output of the phase accumulator results in 0 Hz output from
the DDS. As long as this bit is set high, the frequency and phase
accumulators are cleared, resulting in 0 Hz output. To return to
previous DDS operation, CLR ACC2 must be set to logic low.
CHIRP (MODE 011)
Chirp mode is also known as pulsed FM. Most chirp systems
use a linear FM sweep pattern, but the AD9852 can also support
nonlinear patterns. In radar applications, use of chirp or pulsed
FM allows operators to significantly reduce the output power
needed to achieve the same result a single frequency radar
system produces. Figure 41 represents a very low resolution
nonlinear chirp that demonstrates the different slopes created
by varying the time steps (ramp rate) and frequency steps (delta
frequency word).
The AD9852 permits precise, internally generated linear,
or externally programmed nonlinear, pulsed or continuous
FM over the complete frequency range, duration, frequency
resolution, and sweep direction(s). All of these options are user
programmable. A block diagram of the FM chirp components
is shown in Figure 40.
F1
F2
0
FREQUENCY
MODE
TW1
TW2
FSK DATA
F1
F2
000 (DEFAULT)
0
010 (RAMPED FSK)
I/O UD CLK
00634-039
Figure 39. Effect of Premature Ramped FSK Data
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| X24-009-DK | KIT DEV 2.4GHZ 9600BPS W/RPSMA |
| 0622022510 | TOOL INSERTION 30POS 3ROWS |
| TC70V3I32K7680 | OSCILLATOR 32.7680 KHZ 1.5V SMD |
| TC70M3I32K7680 | OSCILLATOR 32.7680 KHZ 1.8V SMD |
| TC70N3I32K7680 | OSCILLATOR 32.7680 KHZ 2.5V SMD |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9853 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Programmable Digital OPSK/16-QAM Modulator |
| AD9853-45PCB | 制造商:AD 制造商全稱:Analog Devices 功能描述:Programmable Digital OPSK/16-QAM Modulator |
| AD9853-65PCB | 制造商:AD 制造商全稱:Analog Devices 功能描述:Programmable Digital OPSK/16-QAM Modulator |
| AD9853AS | 制造商:Analog Devices 功能描述: 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AD9854 | 制造商:AD 制造商全稱:Analog Devices 功能描述:CMOS 300 MHz Quadrature Complete-DDS |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。